ADPA1106ACGZN-R7 datasheet(14/19 Pages) AD

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Data Sheet

ADPA1106

THEORY OF OPERATION

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Rev. 0 | 14 of 19

The ADPA1106 is a GaN power amplifier that delivers 46 dBm

(40 W) of pulsed power. The device consists of two cascaded gain

stages. A simplified basic block diagram is shown in Figure 51.

The recommended dc bias conditions put the device into deep

Class AB operation, allowing an RF PIN of 21 dBm to produce a

typical pulsed POUT and PAE of 46 dBm and 56%, respectively,

across the 2.7 GHz to 3.5 GHz frequency range. The bias voltage

applied to the VDD1 and VDD2 pins bias the drains of the first and

second gain stages, respectively (the VDD1 and VDD2 must be tied

together).

The dc voltages applied to the VGG1 and VGG2 pins bias the gates

of the first and second gain stages, respectively, allowing control of

the drain currents for each stage (the VGG1 and VGG2 pins must

be tied together).

The ADPA1106 has single-ended RFIN and RFOUT ports that are

dc blocked. The impedance of these ports is nominally 50 Ω over

the 2.7 GHz to 3.5 GHz operating frequency range. Consequently,

the ADPA1106 can be directly inserted into a 50 Ω system without

the need for external impedance matching components or ac cou-

pling capacitors.

A portion of the RF output signal (RFOUT) is directionally coupled

to a diode to detect the RF POUT. When the diode is dc biased, it

rectifies the RF power and makes it available as a dc voltage at

VDET. To allow temperature compensation of VDET, the reference

dc voltage detected through an identical diode that is not coupled to

the RF power is available on the VREF pin. The difference of VREF

− VDET provides a temperature compensated detector voltage that

is proportional to the RF POUT.

Figure 51. Basic Block Diagram

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