LT8685SRVPBF datasheet(13/24 Pages) AD

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LT8685S

Rev. 0

For more information www.analog.com

OPERATION

The LT8685S is a 42V input capable quad, monolithic,

step-down regulator which incorporates Analog Device’s

2nd generation Silent Switcher technology to allow fast

switching edges for high efficiency at high switching fre-

quency, while simultaneously achieving good EMI/EMC

performance.

Channels 1 and 2 are designed to provide output currents

up to 2.5A each from an input supply voltage as high as

42V. Channels 3 and 4 are designed to provide output

currents up to 4A each from an input supply voltage as

high as 8V. Higher output currents can be achieved by

combining channels with a single inductor. For example,

channels 1 and 2 can be combined using a single inductor

to provide a regulated output up to 5A. Channels 3 and

4 can be combined using a single inductor to provide a

regulated output up to 8A. Independent VIN pins allow

for the output of one channel to supply the input of the

other channels.

START-UP

When enabled by setting the EN/UVLO voltage above its

threshold, the LT8685S INTVCC regulator charges its out-

put capacitor to supply the internal chip circuitry. Setting

the EN/UVLO above 0.9V (rising) will enable the channel 1

regulator. Setting the EN/UVLO voltage below the UVLO

threshold will put the part in low power shutdown mode

regardless of the state of the other enable pins.

Channels 2, 3 and 4 are enabled by setting their respec-

tive enable pins above 0.9V (rising). When combining

channels, connect the enable pin of the slave channel to

that of the controlling channel. See Combining Channels

in the Applications Information section for further detail.

BUCK REGULATOR OPERATION

Each channel is a monolithic, synchronous step-down

regulator that operates from an independent VIN pin. The

internal top power MOSFET is turned on at the beginning

of each oscillator cycle and turned off when the current

flowing through the top MOSFET reaches a level deter-

mined by the error amplifier. The error amplifier measures

the output voltage through an external resistor divider

tied to the FB pin to control the peak current in the top

switch. The reference of the error amplifier is determined

by the lower of the internal reference and the voltage at

its soft-start (TRK/SSx) pin. While the top MOSFET is

off, the bottom MOSFET is turned on for the remainder

of the oscillator cycle or until the inductor current starts

to reverse. In current overload conditions the bottom

MOSFET will remain on and the next clock cycle will be

delayed until the switch current is reduced.

PRECISION ENABLE PINS

When driven below 0.4V, the EN/UVLO pin will place the

LT8685S into low power shutdown mode. A voltage on

the EN/UVLO pin above 0.9V (rising) will enable channel 1

operation. Channels 2, 3 and 4 are also activated by driv-

ing their respective EN2, EN3 and EN4 pins above 0.9V

(rising).

A precision threshold of 0.8V (falling) allows the EN/UVLO

to be used as an input undervoltage lockout by connecting

a resistor divider between VIN1 and ground. Similarly, a

precision threshold of 0.81V allows EN2, EN3, and EN4

to also be used as input undervoltage lockouts. See the

Applications Information section for more detail.

POWER GOOD COMPARATORS

Each channel has a power good comparator with an open-

drain output that pulls its PG pin low when its feedback

voltage is more than 7.5% above or below the reference

voltage. The PG pin is released when the feedback pin is

within 6% of the reference voltage. The PG outputs are

not valid until INTVCC rises to 2.7V.

SWITCHING FREQUENCY

Each channel operates from a clock provided by an

internal oscillator whose frequency is determined by an

external resistor connected from the RT pin to ground.

By selecting the appropriate external resistor value, the

switching frequency may be configured from 350kHz to

3MHz. See the Applications Information section for fur-

ther frequency selection information.

The oscillator generates four clock phases. When operat-

ing independently, the relative phases of the channels are

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