LT8685SRVPBF datasheet(19/24 Pages) AD

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LT8685S

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

soft-start time, connect a capacitor between the channel’s

TRK/SS pin and ground according to:

tSS =

CSS • VREF

2µA

where 2µA is the TRK/SS pull-up current, CSS is the value

of the capacitor in Farads, and VREF is 0.8V for CH1 and

CH2, 0.7V for CH3 and CH4.

The channel TRK/SSx pins are pulled down through

approximately 300kΩ, which will discharge the external

soft-start capacitor when the part is shut down or during

certain fault conditions.

For output voltage tracking, the channel TRK/SS pin can

be driven by an external voltage source. More specifically,

when driven with a voltage between 0V and the internal

reference level, the TRK/SS pin will override the internal

reference input to the error amplifier thus regulating the

FB voltage to that present on the TRK/SS pin. When TRK/

SS is above the reference level, tracking is disabled, and

the feedback voltage will regulate to the internal reference

voltage.

When combining channels, slave channel TRK/SS pins

should be open.

Power Good Comparators

Each LT8685S channel has a power good comparator with

an open drain output pin, PGx. Each PG pin is pulled low

when the corresponding feedback voltage is either above

or below its reference voltage by more than 7.5%. See the

Electrical Characteristics table for more information on

each channel’s power good thresholds. All PG pins will be

pulled low when the part is shut down. Individual channel

PG pins will be pulled low when their corresponding EN

pin is low.

When combining channels, only the master channel PG

pins are valid. Slave PG pins should be open.

PCB LAYOUT

The LT8685S is specifically designed to minimize EMI/

EMC emissions and to maximize efficiency when switch-

ing at high frequencies.

For proper operation and minimum EMI, care must be

taken during printed circuit board layout. A recommended

board layout is available with the latest LT8685S demo

board. Some general guidelines are available in the

remainder of this section.

Place a local, unbroken ground plane under the application

circuit on the layer closest to the surface layer and con-

nect the exposed GND pad to this layer. The exposed pad

ground connection should be made with the maximum

number of vias possible to reduce thermal and electrical

impedance to the board ground. For best performance,

maximize unbroken board ground planes in the vicinity

of the LT8685S.

The SW and BST nodes should be made as small as

possible to minimize noise coupling to sensitive traces.

Minimize traces connecting to the RT and all FB pins and

provide ground shielding as needed to minimize noise

coupling to these sensitive nodes.

For each buck regulator, place input bypass capacitors

close to the VINx pins with a low impedance connection

to the exposed pad through the ground plane mentioned

above.

The recommended layer use for a 4-layer board is:

Layer 1 (Components): use 2oz (70µm) copper. Unbroken

high frequency/high current routing, including SW and

BST node routing, plus inductor, input, and output capac-

itor placement. Ground fill on the remainder.

Layer 2 (Internal): Unbroken ground plane.

Layer 3 (Internal): Signal routing with ground plane on

remainder.

Layer 4 (Bottom): Use 2oz (70µm) copper. Use for remain-

ing signal routing with ground fill on the remainder.

THERMAL CONSIDERATIONS

The exposed pad is the path for conducting heat from

the silicon die to the PC board and the surrounding air.

For good heat conduction, thermal vias should be placed

under the device to conduct heat down to internal ground

planes and the back side of the board. Multiple small vias

work better than a few large ones as the copper plating of

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