LT8685SRVPBF datasheet(16/24 Pages) AD

16 / 24 page

LT8685S

Rev. 0

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A simplified application schematic showing sharing

between channels 1 and 2 as well as channels 3 and 4 is

given in Figure 3.

APPLICATIONS INFORMATION

The value of R2 is best selected first as this establishes

how much current is in the resistor divider network cal-

culated as based on I = VREF/R2 where VREF is the internal

channel reference voltage. The current should be chosen

such that it is not influenced by anticipated leakage or

noise. R1 can then be calculated from:

= R2 •

VOUTx

VREF

– 1

⎛

⎝⎜

⎞

⎠⎟

CFF can optionally be used to improve the transient

response and stability of the internally compensated feed-

back loops. The values shown in the Typical Applications

section will provide a good starting point for selecting CFF,

though careful evaluation of regulator stability should be

made to ensure adequate design margin.

For the LT8685S’s 42V input capable channels the maxi-

mum allowed programmed output voltage is 14V.

When the 8V input capable channels are combined (chan-

nels 3 and 4), the maximum allowed programmed output

voltage is 4V.

Operating Frequency and Input Voltage Range

Each buck regulator’s, minimum on-time, tON(MIN), and

minimum off-time, tOFF(MIN), impose limitations on the

achievable duty cycle range and operating frequency. For

buck regulators, the duty cycle is calculated as:

VOUTx

VINx

Further, the minimum duty cycle achievable at a given

operating frequency is calculated as:

DMIN = tON(MIN) • fSW

where fSW is the programmed operating frequency.

Figure 3. Simplified Schematic of Channel Sharing

Figure 4. Feedback Resistor Divider

REVERSE INPUT PROTECTION

In some applications, such as battery charging or bat-

tery backup applications, an LT8685S channel output may

be held high when its input is made to either float or is

grounded. If the input to the channel is floated, and the

LT8685S is enabled, then the LT8685S’s internal circuitry

will pull its quiescent current through the SW pin. If the

input is floated, and the LT8685S is disabled, then the

SW pin current will drop to less than 1µA. If the input is

grounded, an input protection diode is required to prevent

reverse current from the output, through the top power

FET body diode (shown in the Block Diagram), out of the

VINx pin to the grounded input.

BUCK REGULATOR COMPONENT SELECTION

Setting the Output Voltages

The output voltages of the buck channels are set with a

resistor divider from the output to the related FBx pin as

shown in Figure 4.

BST3

SW3

FB3

BST4

SW4

FB4

BIAS

BST1

SW1

FB1

BST2

SW2

FB2

EN/UVLO

EN2

VIN1

VIN2

VIN3

VIN4

3V TO 42V

TRK/SS4

TRK/SS3

TRK/SS2

TRK/SS1

SYNC/MODE

VIN

OUT3,4

LT8685S

INTVCC

EN3

PG4

PG3

PG2

PG1

INTVCC

EN4

OUT1

3V TO 8V

INTVCC

OUT1,2

8685S F03

CFF

OPTIONAL

COUT

FBx

SWx

LT8685S

OUT

8685S F04

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