L6711 datasheet(32/38 Pages) STMICROELECTRONICS

32 / 38 page

L6711

32/38

capacitors are preferred.

Use as much VIAs as possible when power traces have to move between different planes on the PCB:

this reduces both parasitic resistance and inductance. Moreover, reproducing the same high-current trace

on more than one PCB layer will reduce the parasitic resistance associated to that connection.

Connect output bulk capacitor as near as possible to the load, minimizing parasitic inductance and resis-

tance associated to the copper trace also adding extra decoupling capacitors along the way to the load

when this results in being far from the bulk capacitor bank.

Figure 24. Power connections and related connections layout guidelines (same for all phases).

18.2 Power Connections Related.

Figure 24 shows some small signal components placement.

■ Gate and phase traces must be sized according to the driver RMS current delivered to the power

mosfet. The device robustness allows managing applications with the power section far from the

controller without losing performances. Anyway, when possible, it is suggested to minimize the distance

between controller and power section.

In addition, since the PHASEx pin is the return path for the high side driver, this pin might be connected

directly to the High Side mosfet Source pin to have a proper driving for this mosfet. For the LS mosfets,

the return path is the PGNDx pin: it can be connected directly to the power ground plane.

■ Bootstrap capacitor must be placed as close as possible to the BOOTx and PHASEx pins to minimize

the loop that is created.

■ Decoupling capacitor from VCC and SGND placed as close as possible to the involved pins.

■ Decoupling capacitor from VCCDRx and PGNDx placed as close as possible to those pins. This

capacitor sustains the peak currents requested by the low-side mosfet drivers.

■ Sensible components must be referred to SGND (when present): frequency set-up resistor ROSC, offset

resistor ROFFSET, TC resistor RTC and OVP resistor ROVP.

■ Star grounding: Connect SGND to PGND plane in a single point to avoid that drops due to the high

current delivered causes errors in the device behavior.

■ An additional ceramic capacitor is suggested to place near HS mosfet drain. This helps in reducing HF

noise.

■ VSEN pin filtered vs. SGND helps in reducing noise injection into device.

■ OUTEN pin filtered vs. SGND helps in reducing false trip due to coupled noise: take care in routing

driving net for this pin in order to minimize coupled noise.

■ PHASE pin spikes. Since the HS mosfet switches hardly, heavy voltage spikes can be observed on the

PHASEx pins. If these voltage spikes overcome the max breakdown voltage of the pin, the device can

CIN

VIN

UGATEx

PHASEx

LGATEx

PGNDx

LOAD

BOOTx

PHASEx

VCC

SGND

+Vcc

CIN

VIN

LOAD

To limit C

BOOT

Extra-Charge

a. PCB power and ground planes areas

b. PCB small signal components placement

L6711 数据表(PDF) 32 Page - STMicroelectronics

L6711 数据表(HTML) 32 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

数据表下载