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L6711

19

CS3+

Channel 3 Current Sense Positive Input pin.

It must be connected through an Rg resistor to the LS mosfet source (or to the GND-side of the

sense resistor placed in series to the LS mosfet) if LS mosfet sense is performed

(CS_SEL=OPEN). Otherwise (CS_SEL=SGND), it must be connected to the phase-side of the

output inductor (or the inductor-side of the sense resistor used and placed between the channel

3 inductor and the output of the converter) through Rg resistor and an R-C network across the

inductor.

The net connecting the pin to the sense point must be routed as close as possible to the CS3-

net in order to couple in common mode any picked-up noise.

20

TC

Temperature Compensation pin.

pensation effect.

Short to SGND to disable the compensation effect.

21

CS_SEL

Current Reading Selection pin, internally 5V pulled-up.

Leave floating to sense current across low-side mosfets or a sense resistor placed in series to

the LS mosfet source. Maximum duty cycle is dynamically limited and Track&Hold is enabled to

assure proper reading of the current.

Short to SGND to read current across inductors or a sense resistor placed in series to the output

inductors. No duty cycle limitation and no Track&Hold performed in this case.

22

OSC/

FAULT

Oscillator pin.

It allows programming the switching frequency of each channel: the equivalent switching fre-

quency at the load side results in being tripled.

Internally fixed at 1.24V, the frequency is varied proportionally to the current sunk (forced) from

(into) the pin with an internal gain of 6kHz/

µA (See relevant section for details).

If the pin is not connected, the switching frequency is 150kHz for each channel (450kHz on the

load).

The pin is forced high (5V Typ.) when an Over/Under Voltage is detected; to recover from this

condition, cycle VCC or the OUTEN pin.

23, 24 to

28

VID5,

VID0-4

Voltage IDentification pins.

Internally pulled-up to 3V, connect to SGND to program a ‘0’ while leave floating to program a ‘1’.

They are used to program the output voltage as specified in Table 5 and Table 6 together with

VID_SEL and to set the OVP/UVP protection thresholds accordingly.

See relevant section for details about DAC selection.

29

VID_SEL

VID_SELect pin. Through this pin it is possible to select the DAC table used for the regulation.

Leave floating to use a VRD10.x compliant DAC (See Table 1) while short to SGND to use a

VRM-Hammer compliant DAC (See Table 2).

See relevant section for details about DAC selection.

30

SS_END Soft start end signal. It is an open collector output, set free after finishing the soft start.

Pull-up with a resistor to a voltage lower than 5V, if not used may be left floating.

31

SGND

All the internal references are referred to this pin. Connect it to the PCB signal ground.

32

PHASE3 Channel 3 HS driver return path. It must be connected to the HS3 mosfet source and provides

the return path for the HS driver of channel 3.

33

UGATE3 Channel 3 HS driver output.

A little series resistor helps in reducing device-dissipated power.

34

BOOT3

Channel 3 HS driver supply. This pin supplies the relative high side driver.

Connect through a capacitor (100nF Typ.) to the PHASE3 pin and through a diode to VCC (cath-

ode vs. boot).

35

PGND3

Channel 3 LS driver return path.

Connect to Power Ground Plane.

36

LGATE3

Channel 3 LS driver output.

A little series resistor helps in reducing device-dissipated power.

37

N.C.

Not internally connected.

Table 4. Pin Function (continued)

N°

Name

Description