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AM6442...ALV 数据表(PDF) 130 Page - Texas Instruments |
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AM6442...ALV 数据表(HTML) 130 Page - Texas Instruments |
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130 / 244 page  7.10.5 Peripherals 7.10.5.1 CPSW3G For more details about features and additional description information on the device Gigabit Ethernet MAC, see the corresponding subsections within Signal Descriptions and Detailed Description sections. Note CPSW3G MDIO0, CPSW3G RMII1, CPSW3G RMII2, and CPSW3G RGMII1 have one or more signals which can be multiplexed to more than one pin. Timing requirements and switching characteristics defined in this section are only valid for specific pin combinations known as IOSETs. Valid pin combinations or IOSETs for these interfaces are shown respectivly in Table 7-31, Table 7-32, and Table 7-33. 7.10.5.1.1 CPSW3G MDIO Timing Table 7-19, Table 7-20, Table 7-21, and Figure 7-22 present timing conditions, requirements, and switching characteristics for CPSW3G MDIO. Table 7-19. CPSW3G MDIO Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.9 3.6 V/ns OUTPUT CONDITIONS CL Output load capacitance 10 470 pF Table 7-20. CPSW3G MDIO Timing Requirements see Figure 7-22 NO. PARAMETER MIN MAX UNIT MDIO1 tsu(MDIO_MDC) Setup time, MDIO[x]_MDIO valid before MDIO[x]_MDC high 90 ns MDIO2 th(MDC_MDIO) Hold time, MDIO[x]_MDIO valid after MDIO[x]_MDC high 0 ns Table 7-21. CPWS3G MDIO Switching Characteristics see Figure 7-22 NO. PARAMETER MIN MAX UNIT MDIO3 tc(MDC) Cycle time, MDIO[x]_MDC 400 ns MDIO4 tw(MDCH) Pulse Duration, MDIO[x]_MDC high 160 ns MDIO5 tw(MDCL) Pulse Duration, MDIO[x]_MDC low 160 ns MDIO7 td(MDC_MDIO) Delay time, MDIO[x]_MDC low to MDIO[x]_MDIO valid -150 150 ns AM6442, AM6441, AM6421, AM6412, AM6411 SPRSP56D – JANUARY 2021 – REVISED JULY 2022 www.ti.com 130 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411 |
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