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AM6441...ALV 数据表(PDF) 198 Page - Texas Instruments |
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AM6441...ALV 数据表(HTML) 198 Page - Texas Instruments |
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198 / 244 page  Table 7-113. PRU_ICSSG PRU Timing Requirements – Sigma Delta Mode (continued) see Figure 7-96 and Figure 7-97 NO. PARAMETER DESCRIPTION MIN MAX UNIT PRSD2H tw(SD_CLKH) Pulse duration, SDx_CLK high 20 ns PRSD3 tsu(SD_D-SD_CLK) Setup time, SDx_D valid before SDx_CLK active edge 10 ns PRSD4 th(SD_CLK-SD_D) Hold time, SDx_D valid before SDx_CLK active edge 5 ns SDx_CLK PRU_TIMING_07 PRSD2H PRSD2L PRSD4 PRSD3 SDx_D PRSD1 Figure 7-96. PRU_ICSSG PRU SD_CLK Falling Active Edge SDx_CLK PRSD2L PRSD3 PRSD4 PRU_TIMING_08 SDx_D Figure 7-97. PRU_ICSSG PRU SD_CLK Rising Active Edge Table 7-114. PRU_ICSSG PRU Timing Requirements – Peripheral Interface Mode see Figure 7-98 NO. PARAMETER DESCRIPTION MIN MAX UNIT PRPIF1 tw(PIF_DATA_INH) Pulse duration, PIF_DATA_IN high 2 + 0.475*(4*P) (1) ns PRPIF2 tw(PIF_DATA_INL) Pulse duration, PIF_DATA_IN low 2 + 0.475*(4*P) (1) ns (1) P = 1x (or TX) clock period in ns, defined by PRUn_ED_TX_DIV_FACTOR and PRUn_ED_TX_DIV_FACTOR_FRAC in the ICSSG_PRUn_ED_TX_CFG_REG register. PRUn represents the respective PRU0 or PRU1 instance. PIF_DATA_IN PRPIF1 PRUPIF_TIMING_01 PRPIF2 Figure 7-98. PRU_ICSSG PRU Peripheral Interface Timing Requirements AM6442, AM6441, AM6421, AM6412, AM6411 SPRSP56D – JANUARY 2021 – REVISED JULY 2022 www.ti.com 198 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411 |
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