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AM6412...ALV 数据表(PDF) 62 Page - Texas Instruments

部件名 AM6412...ALV
功能描述  AM64x Sitara™ Processors
PDF  244 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

AM6412...ALV 数据表(HTML) 62 Page - Texas Instruments

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6.3.4 DDRSS
6.3.4.1 MAIN Domain
Table 6-8. DDRSS0 Signal Descriptions
SIGNAL NAME [1]
PIN TYPE [2]
DESCRIPTION [3]
ALV PIN [4]
DDR0_ACT_n
O
DDRSS Activation Command
H2
DDR0_ALERT_n
IO
DDRSS Alert
H1
DDR0_CAS_n
O
DDRSS Column Address Strobe
J5
DDR0_PAR
O
DDRSS Command and Address Parity
K5
DDR0_RAS_n
O
DDRSS Row Address Strobe
F6
DDR0_WE_n
O
DDRSS Write Enable
H4
DDR0_A0
O
DDRSS Address Bus
D2
DDR0_A1
O
DDRSS Address Bus
C5
DDR0_A2
O
DDRSS Address Bus
E2
DDR0_A3
O
DDRSS Address Bus
D4
DDR0_A4
O
DDRSS Address Bus
D3
DDR0_A5
O
DDRSS Address Bus
F2
DDR0_A6
O
DDRSS Address Bus
J2
DDR0_A7
O
DDRSS Address Bus
L5
DDR0_A8
O
DDRSS Address Bus
J3
DDR0_A9
O
DDRSS Address Bus
J4
DDR0_A10
O
DDRSS Address Bus
K3
DDR0_A11
O
DDRSS Address Bus
J1
DDR0_A12
O
DDRSS Address Bus
M5
DDR0_A13
O
DDRSS Address Bus
K4
DDR0_BA0
O
DDRSS Bank Address
G4
DDR0_BA1
O
DDRSS Bank Address
G5
DDR0_BG0
O
DDRSS Bank Group
G2
DDR0_BG1
O
DDRSS Bank Group
H3
DDR0_CAL0 (1)
A
IO Pad Calibration Resistor
H5
DDR0_CK0
O
DDRSS Clock
F1
DDR0_CK0_n
O
DDRSS Negative Clock
E1
DDR0_CKE0
O
DDRSS Clock Enable
F4
DDR0_CKE1
O
DDRSS Clock Enable
F3
DDR0_CS0_n
O
DDRSS Chip Select 0
E3
DDR0_CS1_n
O
DDRSS Chip Select 1
E4
DDR0_DM0
IO
DDRSS Data Mask
B2
DDR0_DM1
IO
DDRSS Data Mask
M2
DDR0_DQ0
IO
DDRSS Data
A3
DDR0_DQ1
IO
DDRSS Data
A2
DDR0_DQ2
IO
DDRSS Data
B5
DDR0_DQ3
IO
DDRSS Data
A4
DDR0_DQ4
IO
DDRSS Data
B3
DDR0_DQ5
IO
DDRSS Data
C4
DDR0_DQ6
IO
DDRSS Data
C2
DDR0_DQ7
IO
DDRSS Data
B4
DDR0_DQ8
IO
DDRSS Data
N5
DDR0_DQ9
IO
DDRSS Data
L4
AM6442, AM6441, AM6421, AM6412, AM6411
SPRSP56D – JANUARY 2021 – REVISED JULY 2022
www.ti.com
62
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Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411



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