AM6412...ALV datasheet(102/244 Pages) TI

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over operating junction temperature range (unless otherwise noted)

SUPPLY NAME

DESCRIPTION

MIN(1)

NOM

MAX(1)

UNIT

VDDSHV5

Dual-voltage IO supply

1.8-V operation

1.71

1.8

1.89

3.3-V operation

3.135

3.3

3.465

Operating junction temperature range

Extended

-40

105

°C

(1)

The voltage at the device ball must never drop below the MIN voltage or rise above the MAX voltage for any amount of time during

normal device operation.

(2)

VDD_MMC0 and VDD_DLL_MMC0 must be connected to the same power source as VDD_CORE when MMC0 is not used. In this

case, VDD_MMC0 and VDD_DLL_MMC0 may be operated at a nominal voltage of 0.75 or 0.85.

(3)

VDDS_DDR and VDDS_DDR_C shall be sourced from the same power source.

(4)

The VMON_VSYS pin provides a way to monitor the system power supply. For more information, see Section 9.3.4, System Power

Supply Monitor Design Guidelines.

(5)

An external resistor divider is required to limit the voltage applied to this device pin. For more information, see Section 9.3.3, USB

Design Guidelines.

(6)

The USB0_ID pin is connected to analog circuits in the USB0 PHY. The analog circuits source a known current while measuring

voltage, to determine the resistance value (RID), if connected to VSS through a resistor. This pin should be connected to VSS for USB

host operation, or left unconnected for USB peripheral operation, and should never be connected to any external voltage source.

7.5 Operating Performance Points

This section describes the operating conditions of the device. This section also contains the description of each

Operating Performance Point (OPP) for processor clocks and device core clocks.

Table 7-1 describes the maximum supported frequency per speed grade for the device.

Table 7-1. Speed Grade Maximum Frequency

DEVICE

MAXIMUM FREQUENCY (MHz)

SPEED

GRADE

A53SS

R5FSS

M4FSS

CBASS0

ICSSG

DMSC-L

DDR4(1)

LPDDR4(1)

AM64x

1000

800

400

250

333

TBD

800 (DDR-1600)

800 (LPDDR-1600)

AM64x

800

400

250

TBD

800 (DDR-1600)

800 (LPDDR-1600)

(1)

Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation.

Refer to AM64x\AM243x DDR Board Design and Layout Guidelines for the proper PCB implementation to achieve maximum DDR

frequency.

7.6 Power Consumption Summary

For information on the device power consumption contact your TI Representative.

7.7 Electrical Characteristics

Note

The interfaces or signals described in Section 7.7.1 through Section 7.7.10 correspond to the

interfaces or signals available in multiplexing mode 0 (Primary Function).

All interfaces or signals multiplexed on the balls described in these tables have the same DC electrical

characteristics, unless multiplexing involves a PHY and GPIO combination, in which case different DC

electrical characteristics are specified for the different multiplexing modes (Functions).

7.7.1 I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

1.8 V MODE

VIL

Input Low Voltage

0.3 × VDD

(1)

VILSS

Input Low Voltage Steady State

0.3 × VDD

(1)

VIH

Input High Voltage

0.7 × VDD

(1)

VIHSS

Input High Voltage Steady State

0.7 × VDD

(1)

AM6442, AM6441, AM6421, AM6412, AM6411

SPRSP56D – JANUARY 2021 – REVISED JULY 2022

www.ti.com

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