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AM6412...ALV 数据表(PDF) 166 Page - Texas Instruments |
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AM6412...ALV 数据表(HTML) 166 Page - Texas Instruments |
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166 / 244 page  NO.(1) (6) PARAMETER DESCRIPTION MODE MIN MAX UNIT I4 tw(SCLL) Pulse duration, SCL low Standard 4700 ns Fast 1300 ns I5 tw(SCLH) Pulse duration, SCL high Standard 4000 ns Fast 600 ns I6 tsu(SDAV-SCLH) Setup time, SDA valid before SCL high Standard 250 ns Fast 100 (2) ns I7 th(SCLL-SDAV) Hold time, SDA valid after SCL low Standard 0 (3) 3450 (4) ns Fast 0 (3) 900 (4) ns I8 tw(SDAH) Pulse duration, SDA high between STOP and START conditions Standard 4700 ns Fast 1300 ns I9 tr(SDA) Rise time, SDA Standard 1000 ns Fast 20*(Vdd/ 5.5V) (5)(7) 300 (3)(7) ns I10 tr(SCL) Rise time, SCL Standard 1000 ns Fast 20*(Vdd/ 5.5V) (5)(7) 300 (3)(7) ns I11 tf(SDA) Fall time, SDA Standard 300 ns Fast 20*(Vdd/ 5.5V) (5)(7) 300 (3)(7) ns I12 tf(SCL) Fall time, SCL Standard 300 ns Fast 20*(Vdd/ 5.5V) 300 ns I13 tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) Standard 4000 ns Fast 600 ns I14 tw(SP) Pulse duration, spike (must be supressed) Standard ns Fast 0 50 ns I15 tskew Skew Standard 3 ns Fast 3 ns I16 Cb Capacitive load for each bus line Standard 400 pF Fast 400 pF (1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the devive is powered down. (2) A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns (according to the Standard-mode I2C-Bus Specification) before the SCL line is released. (3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. (4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal. (5) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed (6) Software must properly configure the I2C module registers to achieve the timings shown in this table. See the device TRM for details. (7) These timings apply only to I2C0 and MCU_I2C0. I2C[3:1] and MCU_I2C1 use standard LVCMOS buffers to emulate open-drain buffers and their rise/fall times should be referenced in the device IBIS model. Table 7-59. Timing Requirements for I2C HS–Mode NO. PARAMETER DESCRIPTION CAPACITANCE MIN MAX UNIT I1 tc(SCL) Cycle time, SCL 100 pF Max 294 ns 400 pF Max 588 ns I2 tsu(SCLH-SDAL) Setup time, SCL high before SDA low (for a repeated START condition) 100 pF Max 160 ns 400 pF Max 160 ns I3 th(SDAL-SCLL) Hold time, SCL low after SDA low (for a START and a repeated START condition) 100 pF Max 160 ns 400 pF Max 160 ns AM6442, AM6441, AM6421, AM6412, AM6411 SPRSP56D – JANUARY 2021 – REVISED JULY 2022 www.ti.com 166 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411 |
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