H5AN4G4NAFR-RDC datasheet(18/45 Pages) HYNIX

18 / 45 page

Rev. 1.3 / Mar.2016

IDD2N_par

Precharge Standby Current with CA parity enabled

Same definition like for IDD2N, CA parity enabled3

IDD2P

Precharge Power-Down Current CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 81; AL:

0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: stable at

0; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT:

Enabled in Mode Registers2; ODT Signal: stable at 0

IPP2P

Precharge Power-Down IPP Current

Same condition with IDD2P

IDD2Q

Precharge Quiet Standby Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: stable at 1; Command,

Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable

at 1;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT

Signal: stable at 0

IDD3N

Active Standby Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: stable at 1; Command,

Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 5; Data

IO: VDDQ; DM_n: stable at 1;Bank Activity: all banks open; Output Buffer and RTT: Enabled in

Mode Registers2; ODT Signal: stable at 0; Pattern Details: see Table 5

IDD3NA

Active Standby Current (AL=CL-1)

AL = CL-1, Other conditions: see IDD3N

IPP3N

Active Standby IPP Current

Same condition with IDD3N

IDD3P

Active Power-Down Current

CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 81; AL: 0; CS_n: stable at 1; Command,

Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable

at 1; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal:

stable at 0

IPP3P

Active Power-Down IPP Current

Same condition with IDD3P

IDD4R

Operating Burst Read Current

CKE: High; External clock: On; tCK, CL: see Table 1; BL: 82; AL: 0; CS_n: High between RD;

Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to

Table 7; Data IO: seamless read data burst with different data between one burst and the next one

according to Table 7; DM_n: stable at 1; Bank Activity: all banks open, RD commands cycling through

banks: 0,0,1,1,2,2,... (see Table 7); Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal:

stable at 0; Pattern Details: see Table 7

IDD4RA

Operating Burst Read Current (AL=CL-1)

AL = CL-1, Other conditions: see IDD4R

IDD4RB

Operating Burst Read Current with Read DBI

Read DBI enabled3, Other conditions: see IDD4R

IPP4R

Operating Burst Read IPP Current

Same condition with IDD4R

IDDQ4R

(Optional)

Operating Burst Read IDDQ Current

Same definition like for IDD4R, however measuring IDDQ current instead of IDD current

IDDQ4RB

(Optional)

Operating Burst Read IDDQ Current with Read DBI

Same definition like for IDD4RB, however measuring IDDQ current instead of IDD current

H5AN4G4NAFR-RDC 数据表(PDF) 18 Page - Hynix Semiconductor

H5AN4G4NAFR-RDC 数据表(HTML) 18 Page - Hynix Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

数据表下载