H5AN4G4NAFR-RDC datasheet(21/45 Pages) HYNIX

部件名	H5AN4G4NAFR-RDC

功能描述	4Gb DDR4 SDRAM Lead-Free&Halogen-Free (RoHS Compliant)

PDF	45 Pages

Scroll/Zoom	100%

制造商	HYNIX [Hynix Semiconductor]

网页	http://www.skhynix.com/kor/main.do

标志

21 / 45 page

Rev. 1.3 / Mar.2016

NOTE :

1. Burst Length: BL8 fixed by MRS: set MR0 [A1:0=00].

2. Output Buffer Enable

- set MR1 [A12 = 0] : Qoff = Output buffer enabled

- set MR1 [A2:1 = 00] : Output Driver Impedance Control = RZQ/7

RTT_Nom enable

- set MR1 [A10:8 = 011] : RTT_NOM = RZQ/6

RTT_WR enable

- set MR2 [A10:9 = 01] : RTT_WR = RZQ/2

RTT_PARK disable

- set MR5 [A8:6 = 000]

3. CAL enabled : set MR4 [A8:6 = 001] : 1600MT/s

010] : 1866MT/s, 2133MT/s

011] : 2400MT/s

Gear Down mode enabled :set MR3 [A3 = 1] : 1/4 Rate

DLL disabled : set MR1 [A0 = 0]

CA parity enabled :set MR5 [A2:0 = 001] : 1600MT/s,1866MT/s, 2133MT/s

010] : 2400MT/s

Read DBI enabled : set MR5 [A12 = 1]

Write DBI enabled : set :MR5 [A11 = 1]

4. Low Power Array Self Refresh (LP ASR) : set MR2 [A7:6 = 00] : Normal

01] : Reduced Temperature range

10] : Extended Temperature range

11] : Auto Self Refresh

5. IDD2NG should be measured after sync pulse(NOP) input.

H5AN4G4NAFR-RDC 数据表(PDF) 21 Page - Hynix Semiconductor