4

Application hints

4

3

2

1

SDA

SCL

GND

C1

VDD

GND

The device power supply must be provided through the VDD line; a power supply decoupling capacitor C1 (100

nF) must be placed as near as possible to the supply pads of the device. Depending on the application, an

additional capacitor of 4.7 µF could be placed on the VDD line.

The functionality of the device and the measured data outputs are selectable and accessible through the I²C

interface.

All the voltage and ground supplies must be present at the same time to have proper behavior of the IC (refer to

Figure 6).

VDD

Time



VDD Rising / Falling time : 10 µs ~ 100 ms



VDD must be lower than 0.2 V for at least 10 ms during power-off sequence for correct POR

0.2V

Min.10ms

LPS33K

Application hints

DS12817 - Rev 3

page 10/31