When the ODR bits are set to '000' the device is in Power-down mode. When the device is in power-down mode,

almost all internal blocks of the device are switched off to minimize power consumption. The I²C interface is still

active to allow communication with the device. The content of the configuration registers is preserved and output

data registers are not updated, therefore keeping the last data sampled in memory before going into power-down

mode.

If the ONE_SHOT bit in CTRL_REG2 (11h) is set to '1', One-shot mode is triggered and a new acquisition starts

when it is required. Enabling this mode is possible only if the device was previously in power-down mode (ODR

bits set to '000'). Once the acquisition is completed and the output registers updated, the device automatically

enters in power-down mode. The ONE_SHOT bit self-clears itself.

When the ODR bits are set to a value different than '000', the device is in Continuous mode and automatically

acquires a set of data (pressure and temperature) at the frequency selected through the ODR[2:0] bits.

Once the additional low-pass filter has been enabled through the EN_LPFP bit, it is possible to configure the

device bandwidth acting on the LPFP_CFG bit. Refer to the following table for low-pass filter configurations.

EN_LPFP

LPFP_CFG

Additional low-pass filter status

Device bandwidth

0

x

Disabled

ODR/2

1

0

Enabled

ODR/9

1

1

Enabled

ODR/20

The BDU bit is used to inhibit the update of the output registers between the reading of the upper and lower

register parts. In default mode (BDU = ‘0’), the lower and upper register parts are updated continuously. When the

BDU is activated (BDU = ‘1’), the content of the output registers is not updated until PRESS_OUT_H (2Ah) is

read, in order to avoid reading values related to different samples.

LPS33K

CTRL_REG1 (10h)

DS12817 - Rev 3

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