7.3

CTRL_REG2 (11h)

Control register 2

7

6

5

4

3

2

1

0

BOOT

0(1)

0(1)

IF_ADD_INC

0(1)

SWRESET

0(1)

ONE_SHOT

1. This bit must be set to ‘0’ for proper operation of the device.

BOOT

Reboot memory content. Default value: 0

(0: normal mode; 1: reboot memory content).

The bit is self-cleared when the BOOT is completed.

IF_ADD_INC

Register address automatically incremented during a multiple byte access with a serial interface (I²C).

Default value: 1

(0: disable; 1 enable)

SWRESET

Software reset. Default value: 0

(0: normal mode; 1: software reset).

The bit is self-cleared when the reset is completed.

ONE_SHOT

One-shot enable. Default value: 0

(0: idle mode; 1: a new dataset is acquired)

The BOOT bit is used to refresh the content of the internal registers stored in the Flash memory block. At device

power-up the content of the Flash memory block is transferred to the internal registers related to the trimming

functions to allow correct behavior of the device itself. If for any reason the content of the trimming registers is

modified, it is sufficient to use this bit to restore the correct values. When the BOOT bit is set to ‘1’, the content of

the internal Flash is copied inside the corresponding internal registers and is used to calibrate the device. These

values are factory trimmed and they are different for every device. They allow correct behavior of the device and

normally they should not be changed. At the end of the boot process the BOOT bit is set again to ‘0’ by hardware.

The BOOT bit takes effect after one ODR clock cycle.

The IF_ADD_INC bit is enabled to increment the register address automatically during a multiple byte access with

I²C. In order to read the data properly on multiple byte and single byte access, the recommended configuration for

the LPS33K is the following.

•

For multiple byte access, synchronous data reading is only allowed with IF_ADD_INC = 1 and BDU = 0;

•

For single byte access, either synchronous or asynchronous can be used with IF_ADD_INC = 0, but BDU

has to be set to "1" for asynchronous data reading.

SWRESET is the software reset bit. The following device registers (CTRL_REG1 (10h), CTRL_REG2 (11h)) are

reset to the default value if the SWRESET bit is set to '1'. The SWRESET bit returns back to '0' by hardware.

The ONE_SHOT bit is used to start a new conversion when the ODR[2:0] bits in CTRL_REG1 (10h) are set to

‘000’. Writing a ‘1’ in ONE_SHOT triggers a single measurement of pressure and temperature. Once the

measurement is done, the ONE_SHOT bit will self-clear, the new data are available in the output registers, and

the STATUS (27h) bits are updated.

LPS33K

CTRL_REG2 (11h)

DS12817 - Rev 3

page 18/31