5.2.1

I²C operation

The transaction on the bus is started through a START (ST) signal. A start condition is defined as a HIGH-to-LOW

transition on the data line while the SCL line is held HIGH. After this has been transmitted by the master, the bus

is considered busy. The next data byte transmitted after the start condition contains the address of the slave in the

first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the

slave. When an address is sent, each device in the system compares the first seven bits after a start condition

with its address. If they match, the device considers itself addressed by the master.

The slave address (SAD) associated to the LPS33K is 1011101b.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge

pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the

acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each

byte of data received.

The I²C embedded inside the ASIC behaves like a slave device and the following protocol must be adhered to.

After the start condition (ST) a slave address is sent, once a slave acknowledge has been returned (SAK), an 8-

bit sub-address will be transmitted (SUB): the 7 LSB represent the actual register address while the MSB has no

meaning. The IF_ADD_INC bit in CTRL_REG2 (11h) enables sub-address auto increment (IF_ADD_INC is '1' by

default), so if IF_ADD_INC = '1' the SUB (sub-address) will be automatically increased to allow multiple data read/

write.

The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated START (SR) condition

must be issued after the two sub-address bytes; if the bit is ‘0’ (Write) the master will transmit to the slave with

direction unchanged. The following table explains how the SAD+read/write bit pattern is composed, listing all the

possible configurations.

Command

SAD[6:0]

R/W

SAD+R/W

Read

1011101

1

10111011 (BBh)

Write

1011101

0

10111010 (BAh)

Master

ST

SAD + W

SUB

DATA

SP

Slave

SAK

SAK

SAK

Master

ST

SAD + W

SUB

DATA

DATA

SP

Slave

SAK

SAK

SAK

SAK

Master

ST

SAD + W

SUB

SR

SAD + R

NMAK

SP

Slave

SAK

SAK

SAK

DATA

Master

ST

SAD+W

SUB

SR

SAD+R

MAK

MAK

NMAK

SP

Slave

SAK

SAK

SAK

DATA

DATA

DATA

LPS33K

I²C serial interface

DS12817 - Rev 3

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