L9780 datasheet(32/56 Pages) STMICROELECTRONICS

32 / 56 page

Digital interface description

L9780

32/56

DocID026356 Rev 3

6.1

CSN

CSN pin is used to select the device for serial transfer. If CSN is asserted, SO pin exits its tri

state condition and all status information is latched into SPI shift register; register data are

shifted into SI pin and out from SO pin on each subsequent CLK. If CSN is negated, SO pin

is in tri state condition and the fault register is reloaded (latched) with current filtered status

bits. CSN is immune to spurious pulses of 50 ns or shorter (SO pin can exit tri state

condition but no fault clear is applied and no status bit changes). An internal 30 μA pull-up

current is present on CSN pin in order to force the negated condition if a pin open circuit is

present.

6.2

CLK

CLK pin provides to the device the clock signal necessary for serial data transfer. When

CSN is asserted the device latches input data and shall shift output data on CLK rising

edge.

6.3

SI pin is able to receive data from the master microprocessor while CSN is asserted. The

MSB is the first bit and LSB is the last bit of the word received on SI. The input word consists

of 64 bit; follows the description of the SPI input register.

6.3.1

SPI input register

Bit 63 – 60:

These bits are not used and their status is ignored.

Bit 59: REG

The meaning of this bit is to select a specific content for SO register. If REG=‘0’, SO

contains the status register, if REG=‘1’ SO contains the input register. The device sends the

requested information in the next SPI frame.

Default state for this bit after power on reset: 0.

62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

L9780 数据表(PDF) 32 Page - STMicroelectronics