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L9780

Digital interface description

Bit 58: INRCPD

This bit enables (INRCPD=’1’) or disables (INRCPD=’0’) INRC pull-down current.

If the device receives an SPI command in order to modify the status of this bit in the middle

of a measurement cycle, it stores the new information and applies it at the beginning of the

new measurement cycle. The information reported in the output register is the configuration

used in the last measurement cycle.

If the device receives an SPI command in order to modify INRCPD and VCCSEN bits at the

same time, it will perform these two actions in sequence, with a delay between the two

events. In particular if in the input frame INRCPD=’0’ and VCCSEN =’1’, the device disables

INRC pull-down before enabling VCCS, viceversa if in the input frame INRCPD=’1’ and

VCCSEN =’0’, the device disables VCCS before enabling INRC pull-down current.

For correct use of this bit, refer also to Section 5.5.3.

Default state for this bit after power on reset: 0.

Bit 57: STGINRC

This bit enables (STGINRC=’1’) or disables (STGINRC=’0’) short to ground diagnostic on

INRC pin.

Default state for this bit after power on reset: 0.

Bit 56: INRCGAIN

This bit selects the gain of INRC amplifier as follows:

INRCGAIN =’0’ => selected 4.2 gain;

INRCGAIN =’1’ => selected 2.1 gain.

Possible ranges for these gains are specified in section 8.1.2.1.

If the device receives an SPI command in order to modify the gain of INRC amplifier in the

middle of a measurement cycle, it stores the new information and applies it at the beginning

of the new measurement cycle. The value of the gain reported in the output register is the

gain used in the last measurement cycle.

Default state for this bit after power on reset: 0.

Bit 55: TGEN

This bit enables (TGEN=’1’) or disables (TGEN=’0’) VCCS TG switches between TG and

OUT pins.

If the device receives an SPI command in order to modify TGEN bit in the middle of a

measurement cycle, it stores the new information and applies it at the beginning of the new

measurement cycle. TGEN bit value reported in the output register is the value used in the

last measurement cycle.

Default state for this bit after power on reset: 0.

Bit 54: VCCSEN

This bit enables (VCCSEN=’1’) or disables (VCCSEN=’0’) VCCS cell. When VCCSEN=’0’,

VCCS is disabled and the “parking functionality” is active, that means that on C3 pin a

voltage similar to REF2 is present (the range of this voltage is specified in Table 11).

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