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L99MOD50XP 数据表(PDF) 17 Page - STMicroelectronics |
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L99MOD50XP 数据表(HTML) 17 Page - STMicroelectronics |
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17 / 42 page ![]() DS12615 Rev 4 17/42 L99MOD50XP Electrical specifications 41 15.5 RCLK in CLK pull down resistor VCC = 5 V VCLK = 1.5 V 30 60 150 kΩ 15.6 RDI in DI pull down resistor VCC = 5 V VDI = 1.5 V 30 60 150 kΩ 15.7 RPWM1 in PWM1 pull down resistor VCC = 5 V VPWM1= 1.5 V 30 60 150 kΩ 15.8 Cin(1) Input capacitance at input CSN, CLK, DI and PWM1/2 0 V < VCC < 5.3 V10 pF 1. Value of input capacity is not measured in production test. Parameter guaranteed by design. Table 14. Inputs: CSN, CLK, PWM1/2 and DI (continued) Item Symbol Parameter Test condition Min. Typ. Max. Unit Table 15. SDI timing Item Symbol Parameter(1) Test condition Min. Typ. Max. Unit 16.1 tCLK Clock period VCC = 5 V 1000 ns 16.2 tCLKH Clock high time VCC = 5 V 115 ns 16.3 tCLKL Clock low time VCC = 5 V 115 ns 16.4 tset CSN CSN setup time, CSN low before rising edge of CLK VCC = 5 V 400 ns 16.5 tset CLK CLK setup time, CLK high before rising edge of CSN VCC = 5 V 400 ns 16.6 tset DI DI setup time VCC = 5 V 200 ns 16.7 thold DI DI hold time VCC = 5 V 200 ns 16.8 tr in Rise time of input signal DI, CLK, CSN VCC = 5 V 100 ns 16.9 tf in Fall time of input signal DI, CLK, CSN VCC = 5 V 100 ns 1. DI timing parameters tested in production by a passed / failed test: Tj = -40°C / +25°C: SPI communication @ 2 MHz. Tj = +125°C: SPI communication @ 1.25 MHz. Table 16. DO Item Symbol Parameter Test condition Min. Typ. Max. Unit 17.1 VDOL Output low level IDO = -5 mA 0.2VCC V 17.2 VDOH Output high level IDO = 5 mA 0.8 VCC V 17.3 IDOLK Tristate leakage current VCSN = VCC, 0 V < VDO < VCC -10 10 μA 17.4 CDO (1) Tristate input capacitance VCSN = VCC, 0 V < VCC < 5.3 V 10 pF 1. Value of input capacity is not measured in production test. Parameter guaranteed by design. |
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