L99MOD50XP datasheet(31/42 Pages) STMICROELECTRONICS

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DS12615 Rev 4

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L99MOD50XP

SPI - control and status registers

5.3

Control register 2

OUT9 – HS

on/off

If a bit is set, the selected output driver is switched on. If the corresponding PWM enable

bit is set the driver is only activated if PWM1 (PWM2) input signal is high. The outputs of

OUT1-OUT6 are half bridges. If the bits of HS- and LS-driver of the same half bridge are

set, the internal logic prevents that both drivers of this output stage can be switched on

simultaneously in order to avoid a high internal current from VS to GND.

OUT10 – HS

on/off

OUT11 – HS

on/off

8-1

Reserved

Reserved (has to be set to '0')

Table 25. Control register 1 (read/write) (continued)

Bit

Name

Comment

Table 26. Control register 2 (read/write)

Bit

Name

Comment

OUT1 – OCR enable

In case of an over-current event the over-current status bit (Status Register 0) is

set and the output is switched off. If the Over-current Recovery Enable bit (OCR) is

set, the output will be automatically reactivated after a delay time resulting in a

PWM modulated current with a programmable duty cycle (bit 5 of control register

3).

Depending on occurrence of over-current event and internal clock phase it is

possible that one recovery cycle is executed even if this bit is set to zero.

OUT2 – OCR enable

OUT3 – OCR enable

OUT4 – OCR enable

OUT5 – OCR enable

OUT6 – OCR enable

Reserved (has to be set to '0')

OUT1 PWM1 enable

If the PWM1/2 Enable bit is set and the output is enabled (control register 0 or 1)

the output is switched on if PWM1/2 input is high and switched off if PWM1/2 input

is low. OUT5, 8 and OUT10 are controlled by PWM2 input, all other outputs are

controlled by PWM1 input.

OUT2 PWM1 enable

OUT3 PWM1 enable

OUT4 PWM1 enable

OUT5 PWM2 enable

OUT6 PWM1 enable

Reserved

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