L99MOD50XP datasheet(28/42 Pages) STMICROELECTRONICS

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Functional description of the SPI

L99MOD50XP

28/42

DS12615 Rev 4

Description:



GL_ER: Global Error Flag. Failures of Bits 0-6 are always linked to the Global Error

Flag. This flag is generated by an OR combination of all failure events of the device. It

is reflected via the DO pin while CSN is held low and no clock signal is available. The

flag remains as long as CSN is low. This operation does not cause the Communication

Error bit in the <Global Status> to be set. The signal TW bit3 and OL bit1can be

masked.



CO_ER: Communication Error. If the number of clock pulses within the previous frame

is not 24 the frame is ignored and this bit is set.



C_RESET: Chip RESET. If a stuck at ‘1’ on input DI during any SPI frame occurs, or if a

Power On Reset (VCC monitor) occurs. C_RESET resets (‘1’) with any SPI command.

When C_RESET is active (‘0’), the Gate drivers are switched off (resistive path to

source).

After a startup of the circuit the C_RESET is active because of the POR pulse and the

Gate drivers are switched off. The Gate drivers can only be activated after the

C_RESET has been reset with a SPI command.



TSD: Thermal shutdown due to an internal sensor. All the gate drivers and the charge

pump are switched off (resistive path to source). The TSD bit has to be cleared through

a software reset to reactivate the gate drivers and the charge pump.



TW: Thermal Warning. This bit is maskable by configuration register.



UOV_OC: Logical OR among the filtered under-/over-voltage signals and over-current

signals.



OL: Open Load. Logical OR among the filtered under-current signals. This bit is

maskable by configuration register.



NR: Not Ready. After switching the device from standby mode to active mode an

internal timer is started to allow charge-pump to settle before the outputs can be

activated. This bit is cleared automatically after start up time has finished.

Figure 10. Global error flag definition

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