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SM8521

- 16 -

RDB

Valid data

D0-D7

tRHD

tRHA

tRSA

tRSD

tWRD

A0-A20

• External memory access timing (read timing)

Operating condition

(VDD = 4.5 to 5.5 V, TOPR = –10 to 60˚C)

PARAMETER

SYMBOL

UNIT

NOTE

Address setup time

tRSA

tSYS

tSYS + 50

Read data setup time

tRSD

tSYS/2 – 30

RDB signal pulse width

tWRD

tSYS – 50

tSYS

Address hold time

tRHA

Read data hold time

tRHD

MIN.

TYP.

MAX.

NOTE :

1. tSYS : The system clock period (main clock x 1/2) when the

low order 3 bits in the clock change register

FCPUS2-FCPUS0 are 100B.

tRSA : The time between address firm and RDB signal

falling Low level firm.

tRSD : The time between RDB signal firm and input valid

data firm.

tWRD : RDB signal Low level width.

tRHA : The time between RDB signal rising High level firm

and address change.

tRHD : The time between RDB signal rising High level firm

and output data floating.

Load capacitance is 50 pF.

Fig. 5

External Memory Access Timing (Read Timing)

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