SM8521 datasheet(28/56 Pages) SHARP

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SM8521

ABOUT HOU TO USE HALT MODE AND STOP MODE

The chip switches back to the operating mode from

the HALT mode immediately after the wake up

sources are encountered. For this reason, the

HALT mode is more suitable for systems that need

to be immediately woke up frequently. And, all

interrupt sources (other than illegal instruction trap)

can wake up the chip from the HALT mode.

Switching back to the operating mode from the

STOP mode after the wake up sources are

encountered must pass a warming up period. In

addition, the function blocks used by the main-clock

cannot be used in the wake up from STOP mode.

Since the sampling circuit is stopped, it can not

accept the PINT0 input, either.

For this reason, the STOP mode (conserving more

power than the HALT mode) is suitable for systems

that can easily support the longer time that it will

take to get, back to the operating mode (warming

up period) .

In standby mode, I/O ports setting and output level

for output ports are remained.

Before switches to standby mode, in order to

reduce to the current through every pins, set with

program.

Table 4

System State at Standby Mode

HALT MODE

STOP MODE

Transition method

HALT instruction execution

STOP instruction execution

Wake up method

Hardware reset, interrupt

Hardware reset, interrupt∗1

Function

blocks

Stop

Operating

Stop

Operating

Remain∗2

Remain (interruptable)

Operating

The timer used main-clock as counter clock is stop. It

used external clock as counter clock can still operate.

Operating

Stop

Operating

Stop

Operating

Stop

Operating

Stop

CPU

Main-clock

Sub-clock

RAM, register

I/O port

Timer

Capture trigger

UART

LCDC

Waveform

generator

∗1 The interrupts used to wake up the chip from STOP

mode only have the external interrupts and the internal

interrupts generated by operatable Timer, and SIO.

∗2 General registers, control registers, and the other

memory content all are remained. But something will be

changed for the operatable blocks at STOP mode (for

example, interrupt flag register IR0, IR1 content, etc.)

- 28 -

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