SM8521 datasheet(19/56 Pages) SHARP

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SM8521

- 19 -

Clock change register (CKKC)

Clock change register CKKC is an 8-bit readable/

writable register containing the control of system

clock change and the setting of warming up period

after waking up from the STOP mode.

Clock change register CKKC is initialized to 00H

after hardware reset.

Bit 7

Bit 7 : Clock change enable bit (FCPUEN)

Bit 6 : Main-clock stopped bit (MCKSTP)

Main-clock stopped allows switching to sub-clock

used as system clock.

Bits 5 to 3 : System clock selection bits

(FCPUS2-FCPUS0)

Under the bit FCPUEN = ‘1’, if executes the

STOP instruction, the bits will be valid.

Bit 2 : Reserved bit (TFCPU)

Always write ‘0’ to this position. Writing a ‘1’

produces unrealiable operation.

Bits 1 to 0 : Warming up selection bits

(WUPS1-WUPS10)

The bits are able to set the warming up period

of after wake up from STOP mode.

BIT

SYSTEM CLOCK FREQUENCY

000

System clock = (1/32) x main-clock

001

System clock = (1/16) x main-clock

010

System clock = (1/8) x main-clock

011

System clock = (1/4) x main-clock

101, 110

Reserved

100

System clock = (1/2) x main-clock

111

System clock = (1/2) x sub-clock

BIT

WARMING UP PERIOD AFTER STOP

MODE RELEASES

(when main-clock (fCK) = 10 MHz)

218 x main-clock period (26.21 ms)

217 x main-clock period (13.10 ms)

216 x main-clock period (6.553 ms)

215 x main-clock period (3.276 ms)

FCPUEN MCKSTP FCPUS2 FCPUS1 FCPUS0 TFCPU

WUPS1

WUPS0

Fig. 8

SM8521 Clock System (Equivalent Circuit for Clock System Peripheral Blocks)

fCK

Main-clock

1/2

1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2

System clock

fSYS

1/2

f32K

fCK/4

fCK/8 fCK/16 fCK/32

System clock frequency control

Prescaler PRS0 (frequency divider on fCK/2)

Prescaler PRS1 (frequency divider on f32K)

Sub-clock

fc10 fc11 fc12 fc13 fc14 fc15 fc16

fx1

fx2

fx3

fx4

fx5

fx6

fx7

fx8

fCK/2

1/2

fc12 fc13 fc14 fc15

Prescaler PRS2 (frequency divider on fc10)

Warming up counter (frequency divider on fc10)

For warming

up counter

To function blocks

BIT

CONTENT

Disables system clock speed change

Enables system clock speed change

BIT

CONTENT

Main-clock operation

Main-clock stop

SM8521 数据表(PDF) 19 Page - Sharp Corporation

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