STA335BWSQS datasheet(30/70 Pages) STMICROELECTRONICS

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STA335BWSQS

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6.2.5

Channel input mapping

Each channel received via I2S can be mapped to any internal processing channel via the

Channel Input Mapping registers. This allows for flexibility in processing. The default

settings of these registers map each I2S input channel to its corresponding processing

channel.

6.3

Configuration register C (addr 0x02)

6.3.1

DDX® power output mode

The DDX power output mode selects how the DDX output timing is configured.

Different power devices use different output modes.

Table 21.

CnIM

Bit

RST

Name

Description

6RW

C1IM

0: Processing channel 1 receives Left I2S Input

1: Processing channel 1 receives Right I2S Input

7RW

C2IM

0: Processing channel 2 receives Left I2S Input

1: Processing channel 2 receives Right I2S Input

OCRB

Reserved

CSZ3

CSZ2

CSZ1

CSZ0

OM1

OM0

011

Table 22.

Bit

RST

Name

Description

0RW

OM0

Selects configuration of DDX output.

1RW

OM1

Table 23.

Output modes

OM[1,0]

Output stage mode

Drop compensation

Discrete output stage - tapered compensation

Full power mode

Variable drop compensation (CSZx bits)

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