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STA335BWSQS 数据表(PDF) 37 Page - STMicroelectronics |
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STA335BWSQS 数据表(HTML) 37 Page - STMicroelectronics |
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37 / 70 page  STA335BWSQS Register description 37/70 STA335BWSQS can be configured to support different output configurations. For each PWM output channel a PWM slot is defined. The PWM slot always has a time duration of 1/(8 * Fs) seconds. The PWM slot defines the maximum extension for PWM rising and falling edges, that is, rising edge as far as the falling edge cannot range outside PWM slot boundaries. Figure 12. STA335BWSQS output mapping scheme Figure 9. OCFG = 00 (default value) Figure 10. OCFG = 01 Figure 11. OCFG = 10 OCFG = 11 Half Bridge Half Bridge Half Bridge Half Bridge OUT1A OUT1B OUT2A OUT2B Channel 2 Channel 1 LPF LineOut 1 OUT3B LPF LineOut 2 OUT4B OUT4A OUT3A Half Bridge Half Bridge Half Bridge Half Bridge OUT1A OUT1B OUT2A OUT2B Channel 3 Channel 1 Channel 2 Half Bridge Half Bridge Half Bridge Half Bridge OUT1A OUT1B OUT2A OUT2B Channel 2 Channel 1 Power Device OUT3B OUT3A EAPD Channel 3 Half Bridge Half Bridge Half Bridge Half Bridge OUT1A OUT1B OUT2A OUT2B Channel 3 OUT3B OUT4B OUT4A OUT3A Channel 1 Channel 2 DDX™ modulator REMAP DDX1A DDX1B DDX2A DDX2B OUT1A OUT1B OUT2A OUT2B Power Bridge OUT1A OUT1B OUT2A OUT2B DDX3A DDX3B DDX4A DDX4B OUT3A OUT3B OUT4A OUT4B |
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