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STA335BWSQS 数据表(PDF) 34 Page - STMicroelectronics

部件名 STA335BWSQS
功能描述  2.1-channel, high-efficiency digital audio system with QSound QHD®
PDF  70 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STA335BWSQS 数据表(HTML) 34 Page - STMicroelectronics

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Register description
STA335BWSQS
34/70
6.5
Configuration register E (addr 0x04)
6.5.1
Max power correction variable
6.5.2
Max power correction
Setting the MPC bit turns on special processing that corrects the STA335BWSQS power
device at high power. This mode should lower the THD+N of a full DDX system at maximum
power output and slightly below. If enabled, MPC is operational in all output modes except
tapered (OM[1,0] = 01) and binary. When OCFG = 00, MPC will not effect channels 3 and 4,
the line-out channels.
6.5.3
Noise-shaper bandwidth selection
6.5.4
AM mode enable
STA335BWSQS features a DDX processing mode that minimizes the amount of noise
generated in frequency range of AM radio. This mode is intended for use when DDX is
operating in a device with an AM tuner active. The SNR of the DDX processing is reduced to
approximately 83 dB in this mode, which is still greater than the SNR of AM radio.
D7
D6
D5
D4
D3
D2
D1
D0
SVE
ZCE
DCCV
PWMS
AME
NSBW
MPC
MPCV
11
00
001
0
Table 35.
MPCV
Bit
RW
RST
Name
Description
0RW
0
MPCV
0: Use standard MPC coefficient
1: Use MPCC bits for MPC coefficient
Table 36.
MPC
Bit
RW
RST
Name
Description
1RW
1
MPC
1: Enable power bridge correction for THD reduction
near maximum power output.
Table 37.
NSBW
Bit
RW
RST
Name
Description
2
RW
0
NSBW
1: Third order NS
0: Fourth order NS
Table 38.
AME
Bit
RW
RST
Name
Description
3RW
0
AME
0: Normal DDX operation.
1: AM reduction mode DDX operation



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