RAMK060

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Vishay MCB

Revision: 03-May-2022

5

Document Number: 32579

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SSI INTERFACE (Standard Output Format)

Fig. 3 - SSI Chronogram

TABLE 1 - SSI CONNECTOR

PIN NO.

NAME

1VCC power supply

2CLK+

3CLK-

4

DATA+

5

DATA-

6

GND power supply

TABLE 2 - SSI PARAMETERS

PARAMETER

INFORMATION

CLK differential interface

RS422 according to the EIA-RS422

DATA differential interface

Output DATA

Binary two’s complement left aligned

Clock frequency (tclk)

100 kHz to 3 MHz

Data bit status

3

Data bits (angle value)

19

Parity bit

ODD

Time out (time between two requests)

20 μs minimum

TABLE 3 - SSI DATA BITS FORMAT

ANGLE VALUE SSI DATA BITS FORMAT

FRAME BITS (SSI CHRONOGRAM FIG. 3)

FUNCTION

Bit 0

Status bit A1

Bit 1

Status bit A2

Bit 2

Status bit A3

Bit 3

Data MSB

Bit 21

Data LSB

Bit 22

Always = 0

Bit 23

Parity

SSI

CLK+

CLK-

A1

A2

A3

MSBLSBP

Time out

01

2

3

23

18

DATA+

DATA-

456

22

21

20

19

≥ 1 μs

t = 20 μs

t

clk