RAMK060

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Vishay MCB

Revision: 03-May-2022

7

Document Number: 32579

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SPI INTERFACE (Optional)

Fig. 5 - SPI Chronogram

TABLE 7 - SPI CONNECTOR

PIN NO.

NAME

1VCC power supply

2CLK

3DATA

4CS

5NC

6

GND power supply

TABLE 8 - SPI PARAMETERS

PARAMETER

INFORMATION

SPI configuration

Slave mode only

CLK and DATA

TTL 3.3 V or 5 V

Output DATA

Left aligned

Clock frequency (tclk)

Up to 4 MHz

ts (time to start)

1 μs minimum

Data bit status

3

Data bits (angle value)

19

Parity bit

ODD

Time out (time between two requests)

6 μs minimum

TABLE 9 - SPI DATA BITS FORMAT

ANGLE VALUE SPI DATA BITS FORMAT

FRAME BITS (SPI CHRONOGRAM FIG. 5)

FUNCTION

Bit 0

Status bit A1

Bit 1

Status bit A2

Bit 2

Status bit A3

Bit 3

Data MSB

Bit 21

Data LSB

Bit 22

Always = 0

Bit 23

Parity

A1

CPOL = 1

CPHA = 1

A2

A3

MSB

LSB

P

A1

A2

A3

MSB

SPI Slave Mode

Bit 0

Bit 1

Bit 2

Bit 3

Bit 20

Bit 21

Bit 22

Bit 23

ts = 1 µs

tp = 6 µs

tclk