Copyright © Bridgetek Pte Ltd

20

FT801 Embedded Video Engine Datasheet

Version 1.3

Document Reference No.: BRT_000001

Clearance No.: BRT#003

REG_DITHER enables colour dither; the default is enabled. This option improves the half-tone appearance

on displays. Internally, the graphics engine computes the colour values at an 8 bit precision; however,

the LCD colour at a lower precision is sufficient. The FT801 output is only 6 bits per colour in 6:6:6

formats and a 2X2 dither matrix allow the truncated bits to contribute to the final colour values.

REG_OUTBITS gives the bit width of each colour channel, the default is 6, 6, 6 bits for each RGB colour.

A lower value means fewer bits are output for each channel allowing dithering on lower precision LCD

displays.

REG_SWIZZLE controls the arrangement of the output colour pins, to help the PCB route different LCD

panel arrangements. Bit 0 of the register causes the order of bits in each colour channel to be reversed.

Bits 1-3 control the RGB order. Setting Bit 1 causes R and B channels to be swapped. Setting Bit 3 allows

rotation to be enabled. If Bit 3 is set, then (R,G,B) is rotated right if bit 2 is one, or left if bit 2 is zero.

REG_SWIZZLE

PINS

b3 b2 b1 b0 R7, R6, R5,

R4, R3, R2

G7, G6, G5,

G4, G3, G2

B7, B6, B5, B4,

B3, B2

0

X

0

0

R[7:2]

G[7:2]

B[7:2]

Power on Default

0

X

0

1

R[2:7]

G[2:7]

B[2:7]

0

X

1

0

B[7:2]

G[7:2]

R[7:2]

0

X

1

1

B[2:7]

G[2:7]

R[2:7]

1

0

0

0

G[7:2]

B[7:2]

R[7:2]

1

0

0

1

G[2:7]

B[2:7]

R[2:7]

1

0

1

0

G[7:2]

R[7:2]

B[7:2]

1

0

1

1

G[2:7]

R[2:7]

B[2:7]

1

1

0

0

B[7:2]

R[7:2]

G[7:2]

1

1

0

1

B[2:7]

R[2:7]

G[2:7]

1

1

1

0

R[7:2]

B[7:2]

G[7:2]

1

1

1

1

R[2:7]

B[2:7]

G[2:7]

Table 4-10 REG_SWIZZLE RGB Pins Mapping

4.5

Miscellaneous Control

4.5.1 Backlight Control Pin

The backlight control pin is a pulse width modulated (PWM) signal controlled by two registers:

REG_PWM_HZ and REG_PWM_DUTY. REG_PWM_HZ specifies the PWM output frequency, the range is

250-10000 Hz. REG_PWM_DUTY specifies the duty cycle; the range is 0-128. A value of 0 means that the

PWM is completely off and 128 means completely on.

4.5.2 DISP Control Pin

The DISP pin is a general purpose output that can be used to enable or as a reset control to LCD display

panel. The pin is controlled by writing to Bit 7 of REG_GPIO register.

4.5.3 General Purpose IO pins

The GPIO1 and GPIO0 pins are default inputs. Write '1' to Bit 1 and 0 of REG_GPIO_DIR to change to

output pins respectively. In I²C mode the GPIO0 is used as SA2 and is not available as GPIO.

GPIO1 and GPIO0 are read from or write to bit 1 and 0 of REG_GPIO register. GPIO1 is recommended to

be used as shutdown control for audio power amplifier.

4.5.4 Pins Drive Current Control

The output drive current of output pins can be changed as per the following table by writing to bit[6:2] of

REG_GPIO register:

REG_GPIO

Bit[6:5]

Bit[4]

Bit[3:2]

Value

00b#

01b

10b

11b

0b#

1b

00b#

01b

10b

11b

Drive

4mA

8mA

12mA

16mA

4mA

8mA

4mA

8mA

12mA

16mA