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FT801Q-R 数据表(PDF) 11 Page - Bridgetek Pte Ltd. |
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FT801Q-R 数据表(HTML) 11 Page - Bridgetek Pte Ltd. |
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11 / 44 page ![]() Copyright © Bridgetek Pte Ltd 11 FT801 Embedded Video Engine Datasheet Version 1.3 Document Reference No.: BRT_000001 Clearance No.: BRT#003 4.1.1 SPI Interface The SPI slave interface operates up to 30MHz. Only SPI mode 0 is currently supported. Refer to section 6.3.2 for detailed timing specification. The SPI interface is selected when the MODE pin is tied to GND. 4.1.2 I²C Interface The I²C slave interface operates up to 3.4MHz, supporting standard-mode, fast-mode, fast-mode plus and high-speed mode. Refer to section 6.3.3 for detailed timing specification. The I²C device address is configurable between 20h to 27h depending on the I²C_SA[2:0] pin setting, i.e. the 7-bit I2C slave address is 0b’0100A2A1A0. The I²C interface is selected when the MODE pin is tied to VCCIO. 4.1.3 Serial Data Protocol The FT801 appears to the host MPU/MCU as a memory-mapped SPI or I²C device. The host communicates with the FT801 using reads and writes to a large (4 megabyte) address space. Within this address space are dedicated areas for graphics, audio and touch control. Refer to section 5 for the detailed memory map. The host reads and writes the FT801 address space using SPI or I²C transactions. These transactions are memory read, memory write and command write. Serial data is sent by the most significant bit first. For I²C transactions, the same byte sequence is encapsulated in the I²C protocol. For SPI operation, each transaction starts with CS_N goes low, and ends when CS_N goes high. There’s no limit on data length within one transaction, as long as the memory address is continuous. 4.1.4 Host Memory Read For SPI memory read transaction, the host sends two zero bits, followed by the 22-bit address. This is followed by a dummy byte. After the dummy byte, the FT801 responds to each host byte with read data bytes. Byte n Table 4-1 Host memory read transaction (SPI) For I2C memory read transaction, bytes are packed in the I2C protocol as follow: [start] <DEVICE ADDRESS + write bit> <00b+Address[21:16]> <Address[15:8]> <Address[7:0]> [restart] <DEVICE ADDRESS + read bit> <Read data byte 0> .... <Read data byte n> [stop] 7 6 5 4 3 2 1 0 0 0 Address [21:16] Address [15:8] Address [7:0] Dummy byte Byte 0 Read Data Write Address |
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