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FT801Q-R 数据表(PDF) 27 Page - Bridgetek Pte Ltd.

部件名 FT801Q-R
功能描述  Embedded Video Engine
PDF  44 Pages
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制造商  BRIDGETEK [Bridgetek Pte Ltd.]
网页  https://brtchip.com/
标志 BRIDGETEK - Bridgetek Pte Ltd.

FT801Q-R 数据表(HTML) 27 Page - Bridgetek Pte Ltd.

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FT801 Embedded Video Engine Datasheet
Version 1.3
Document Reference No.: BRT_000001
Clearance No.: BRT#003
Figure 4-9 Power State Transition
4.8.3.1 ACTIVE state
In ACTIVE state, the FT801 is in normal operation. The crystal oscillator and PLL are functioning. The
system clock applied to the FT801 core engines is enabled.
4.8.3.2 STANDBY state
In STANDBY state, the crystal oscillator and PLL remain functioning; the system clock applied to the
FT801 core engines is disabled. All register contents are retained.
4.8.3.3 SLEEP state
In SLEEP state, the crystal oscillator, PLL and system clock applied to the FT801 core engines are
disabled. All register contents are retained.
4.8.3.4 POWERDOWN state
In POWERDOWN state, the internal 1.2V regulator supplying the core digital logic, the crystal oscillator,
the PLL and the system clock applied to the FT801 core is disabled. All register contents are lost and
reset to default when the chip is next switched on.
4.8.3.5 Wake up to ACTIVE from other power states
Wake up from POWERDOWN state requires the host to pull the PD_N pin down and release, a low to high
transition enables the 1.2V regulator. POR generated when 1.2V is stable and FT801 will switch to
STANDBY mode after internal oscillator and PLL are up (maximum 20ms from PD_N rising edge). The
clock enable sequence mentioned in section 4.2.3 shall be executed to proper enable the system clock.
From SLEEP state, host MPU reads at memory address 0 to wake the FT801 into ACTIVE state. Host
needs to wait for at least 20ms before accessing any registers or commands. This is to guarantee the
crystal oscillator and PLL are up and stable.
From STANDBY state, host MPU reads at memory address 0 to wake the FT801 into ACTIVE state. Host
can immediately access any register or command.
POWERDOWN
STANDBY
SLEEP
VCC/VCCIO
Power ON
Toggle PD_N from high
to low
ACTIVE
Toggle PD_N from low
to high
Toggle PD_N from high
to low
Toggle PD_N from high to low or
Write command “POWERDOWN”
Write command “SLEEP”
Write command
“STANDBY”
Dummy Read “0”
Dummy Read “0”



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