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FT801Q-R 数据表(PDF) 34 Page - Bridgetek Pte Ltd.

部件名 FT801Q-R
功能描述  Embedded Video Engine
PDF  44 Pages
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制造商  BRIDGETEK [Bridgetek Pte Ltd.]
网页  https://brtchip.com/
标志 BRIDGETEK - Bridgetek Pte Ltd.

FT801Q-R 数据表(HTML) 34 Page - Bridgetek Pte Ltd.

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34
FT801 Embedded Video Engine Datasheet
Version 1.3
Document Reference No.: BRT_000001
Clearance No.: BRT#003
6.3.2 Host Interface SPI Mode 0
Figure 6-1 SPI Interface Timing
Parameter
Description
VCC(I/O)=1.8V
VCC(I/O)=2.5V
VCC(I/O)=3.3V
Units
Min
Max
Min
Max
Min
Max
Tsclk
SPI clock period
60
-
40
-
33
-
ns
Tsclkl
SPI clock low duration
25
-
16
-
13
-
ns
Tsclkh
SPI clock high
duration
25
-
16
-
13
-
ns
Tsac
SPI access time
16
-
16
-
16
-
ns
Tisu
Input Setup
12
-
11
-
11
-
ns
Tih
Input Hold
3
-
3
-
3
-
ns
Tzo
Output enable delay
0
30
0
20
0
16
ns
Toz
Output disable delay
0
30
0
20
0
16
ns
Tod
Output data delay
0
24
0
15
0
12
ns
Tcsnh
CSN hold time
0
-
0
-
0
-
ns
Table 6-7 SPI Interface Timing Specification
6.3.3 Host Interface I2C Mode Timing
Parameter
Description
Standard-
mode
Fast-mode
Fast-plus
mode
High speed
mode
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Fscl
I2C SCL clock
frequency
0
100
0
400
0
1000
0
3400
kHz
Tscll
clock low period
4.7
-
1.3
-
0.5
-
0.16
-
µs
Tsclh
clock high
period
4.0
-
0.6
-
0.26
-
0.06
-
µs
Tsu
Data setup time
250
-
100
-
50
-
10
-
ns
Thd
Data hold time
0
-
0
-
0
-
0
70
ns
Tr
Rise time
-
1000
-
300
-
120
10
40
ns
Tf
Fall time
-
300
-
300
-
120
10
40
ns
Table 6-8 I2C Interface Timing
6.3.4 RGB Video Timing
Parameter
Description
VCC=3.3V
Units
Min
Typ
Max
Tpclk
Pixel Clock period
78
104
-
ns
Tpclkdc
Pixel Clock duty cycle
40
-
60
%
Thc
Hsync to Clock
30
-
-
ns
Thwh
HSYNC width
(REG_HSYNC1-REG_HSYNC0)
1
41
-
Tpclk
Tvwh
VSYNC width
(REG_VSYNC1-REG_VSYNC0)
1
10
-
Th
Th
HSYNC Cycle
(REG_HCYCLE)
-
525
-
Tpclk
Tvsu
VSYNC setup
30
-
-
ns



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