AD7453BRT-R2 datasheet(4/20 Pages) AD

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AD7453

TIMING SPECIFICATIONS1, 2

(VDD = 2.7 V to 5.25 V, fSCLK = 10 MHz, fS = 555 kSPS, VREF = 2.5 V, TA = TMIN to TMAX,

unless otherwise noted.)

Parameter

Limit at TMIN, TMAX

Unit

Description

fSCLK

kHz min

MHz max

tCONVERT

¥ tSCLK

tSCLK = 1/fSCLK

1.6

ms max

tQUIET

ns min

Minimum Quiet Time between the End of a Serial Read and the Next Falling

Edge of

ns min

Minimum

CS Pulse Width

ns min

CS Falling Edge to SCLK Falling Edge Setup Time

ns max

Delay from

CS Falling Edge Until SDATA Three-State Disabled

ns max

Data Access Time After SCLK Falling Edge

0.4 tSCLK

ns min

SCLK High Pulse Width

0.4 tSCLK

ns min

SCLK Low Pulse Width

ns min

SCLK Edge to Data Valid Hold Time

ns min

SCLK Falling Edge to SDATA Three-State Enabled

ns max

SCLK Falling Edge to SDATA Three-State Enabled

tPOWER-UP

ms max

Power-Up Time from Full Power-Down

NOTES

1Sample tested at 25

∞C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.

2See Figure 1 and the Serial Interface section.

3Mark/Space ratio for the SCLK input is 40/60 to 60/40.

4Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V with V

DD = 5 V and time for an output to cross

0.4 V or 2.0 V for VDD = 3 V.

8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated

back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t 8, quoted in the timing characteristics is the true bus relinquish

time of the part and is independent of the bus loading.

6See Power-Up Time section.

Specifications subject to change without notice.

SCLK

SDATA

tQUIET

tCONVERT

345

DB11

DB10

DB2

DB1

DB0

THREE-STATE

4 LEADING ZEROS

Figure 1. AD7453 Serial Interface Timing Diagram

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