REV. 0

–10–

AD7453

CIRCUIT INFORMATION

The AD7453 is a 12-bit, low power, single supply, successive

approximation analog-to-digital converter (ADC) with a pseudo

differential analog input. It operates with a single 2.7 V to

5.25 V power supply and is capable of throughput rates up to

555 kSPS when supplied with a 10 MHz SCLK. It requires an

The AD7453 has an on-chip differential track-and-hold amplifier,

a successive approximation (SAR) ADC, and a serial interface,

housed in an 8-lead SOT-23 package. The serial clock input

accesses data from the part and provides the clock source for

the successive approximation ADC. The AD7453 features a

power-down option for reduced power consumption between

conversions. The power-down feature is implemented across

the standard serial interface, as described in the Modes of

Operation section.

CONVERTER OPERATION

The AD7453 is a successive approximation ADC based around

two capacitive DACs. Figures 3 and 4 show simplified schematics

of the ADC in the acquisition and conversion phase, respectively.

The ADC is comprised of control logic, an SAR, and two capaci-

tive DACs. In Figure 3 (acquisition phase), SW3 is closed and

SW1 and SW2 are in Position A, the comparator is held in a

balanced condition, and the sampling capacitor arrays acquire

the differential signal on the input.

A

B

SW1

SW3

COMPARATOR

CONTROL

LOGIC

CAPACITIVE

DAC

CAPACITIVE

DAC

SW2

B

A

Figure 3. ADC Acquisition Phase

When the ADC starts a conversion (Figure 4), SW3 will open

and SW1 and SW2 will move to Position B, causing the com-

parator to become unbalanced. Both inputs are disconnected

once the conversion begins. The control logic and the charge

redistribution DACs are used to add and subtract fixed amounts

of charge from the sampling capacitor arrays to bring the com-

parator back into a balanced condition. When the comparator is

rebalanced, the conversion is complete. The control logic

generates the ADC’s output code. The output impedances of

otherwise the two inputs will have different settling times, resulting

in errors.

A

B

SW1

SW3

COMPARATOR

CONTROL

LOGIC

CAPACITIVE

DAC

CAPACITIVE

DAC

SW2

B

A

Figure 4. ADC Conversion Phase

ADC TRANSFER FUNCTION

The output coding for the AD7453 is straight (natural) binary.

The designed code transitions occur at successive LSB values

The ideal transfer characteristic of the AD7453 is shown in

Figure 5.

000...00

0V

ANALOG INPUT

111...11

000...01

111...00

011...11

1LSB

111...10

000...10

Figure 5. Ideal Transfer Characteristic

TYPICAL CONNECTION DIAGRAM

Figure 6 shows a typical connection diagram for the AD7453.

In this setup the GND pin is connected to the analog ground

2.5 V decoupled reference source. The signal source, is con-

with a 1

mF tantalum capacitor in parallel with a 0.1 mF ceramic

capacitor. The reference pin should be decoupled to AGND

with a capacitor of at least 0.1

mF. The conversion result is

output in a 16-bit word with four leading zeros followed by the

MSB of the 12-bit result.

SCLK

SDATA

CS

GND

C/ P

SERIAL

INTERFACE

+2.7V TO +5.25V

SUPPLY

2.5V

AD780

0.1 F

0.1 F

10 F

AD7453

P-TO-P

DC INPUT

VOLTAGE

Figure 6. Typical Connection Diagram