REV. 0

–12–

AD7453

Figure 10 shows a graph of THD versus analog input frequency

for various supply voltages, while sampling at 555 kSPS with an

SCLK of 10 MHz. In this case the source impedance is 10

W.

INPUT FREQUENCY (kHz)

–90

10

100

277

–85

–80

–75

–70

–65

–60

–55

–50

Figure 10. THD vs. Analog Input Frequency for

Various Supply Voltages

DIGITAL INPUTS

The digital inputs applied to the AD7453 are not limited by the

maximum ratings that limit the analog inputs. Instead the digi-

tal inputs applied, i.e.,

CS and SCLK, can go to 7 V and are not

The main advantage of the inputs not being restricted to the

avoided. If

CS or SCLK are applied before V

of latch-up as there would be on the analog inputs if a signal

REFERENCE SECTION

An external source is required to supply the reference to the

AD7453. This reference input can range from 100 mV to 3.5 V.

The specified reference is 2.5 V for the power supply range

2.7 V to 5.25 V. The reference input chosen for an application

should never be greater than the power supply. Errors in the

reference source result in gain errors in the AD7453 transfer func-

tion. A capacitor of at least 0.1

pin. Suitable reference sources for the AD7453 include the

AD780 and the ADR421. Figure 11 shows a typical connection

1

AD780

NC

8

2

NC

7

3

GND

6

4

TEMP

5

OPSEL

TRIM

AD7453*

0.1 F

2.5V

NC

NC

0.1 F

10nF

0.1 F

*ADDITIONAL PINS OMITTED FOR CLARITY

NC = NO CONNECT

SERIAL INTERFACE

Figure 1 shows a detailed timing diagram of the serial inter-

face of the AD7453. The serial clock provides the conversion

clock and also controls the transfer of data from the device

during conversion.

CS initiates the conversion process and

frames the data transfer. The falling edge of

CS puts the track-

and-hold into hold mode and takes the bus out of three-state.

The analog input is sampled and the conversion initiated at this

point. The conversion will require 16 SCLK cycles to complete.

Once 13 SCLK falling edges have occurred, the track-and-hold

will go back into track mode on the next SCLK rising edge, as

shown at Point B in Figure 1. On the 16th SCLK falling edge,

the SDATA line will go back into three-state.

If the rising edge of

CS occurs before 16 SCLKs have elapsed,

the conversion will be terminated and the SDATA line will go

back into three-state.

The conversion result from the AD7453 is provided on the

SDATA output as a serial data stream. The bits are clocked out

on the falling edge of the SCLK input. The data stream of the

AD7453 consists of four leading zeros, followed by 12 bits of

conversion data, provided MSB first. The output coding is

straight (natural) binary.

Sixteen serial clock cycles are required to perform a conversion

and to access data from the AD7453.

CS going low provides the

first leading zero to be read in by the microcontroller or DSP.

The remaining data is then clocked out on the subsequent SCLK

falling edges, beginning with the second leading zero. Thus the

first falling clock edge on the serial clock provides the second

leading zero. The final bit in the data transfer is valid on the

16th falling edge, having been clocked out on the previous (15th)

falling edge. Once the conversion is complete and the data has

been accessed after the 16 clock cycles, it is important to ensure

that, before the next conversion is initiated, enough time is left

to meet the acquisition and quiet time specifications—see the

timing example that follows.