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TDA4AL...ALZQ1 数据表(PDF) 59 Page - Texas Instruments

部件名 TDA4AL...ALZQ1
功能描述  TDA4VE TDA4AL TDA4VL Jacinto™ Processors, Silicon Revision 1.0
PDF  251 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TDA4AL...ALZQ1 数据表(HTML) 59 Page - Texas Instruments

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6.3 Signal Descriptions
6.3.1 ADC
6.3.1.1 MCU Domain
Table 6-3. MCU_ADC Signal Descriptions
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALZ PIN
MCU_ADC_EXT_TRIGGER0
I
ADC Trigger Input
C23, E22, F27
MCU_ADC_EXT_TRIGGER1
I
ADC Trigger Input
E21, F25, F26
Table 6-4. MCU_ADC0 Signal Descriptions
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALZ PIN
MCU_ADC0_AIN0
A
ADC Input 0
L25
MCU_ADC0_AIN1
A
ADC Input 1
K25
MCU_ADC0_AIN2
A
ADC Input 2
M24
MCU_ADC0_AIN3
A
ADC Input 3
L24
MCU_ADC0_AIN4
A
ADC Input 4
L27
MCU_ADC0_AIN5
A
ADC Input 5
K24
MCU_ADC0_AIN6
A
ADC Input 6
M27
MCU_ADC0_AIN7
A
ADC Input 7
M26
Table 6-5. MCU_ADC1 Signal Descriptions
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALZ PIN
MCU_ADC1_AIN0
A
ADC Input 0
P25
MCU_ADC1_AIN1
A
ADC Input 1
R25
MCU_ADC1_AIN2
A
ADC Input 2
P28
MCU_ADC1_AIN3
A
ADC Input 3
P27
MCU_ADC1_AIN4
A
ADC Input 4
N25
MCU_ADC1_AIN5
A
ADC Input 5
P26
MCU_ADC1_AIN6
A
ADC Input 6
N26
MCU_ADC1_AIN7
A
ADC Input 7
N27
6.3.2 DDRSS
6.3.2.1 MAIN Domain
Table 6-6. DDRSS0 Signal Descriptions
SIGNAL NAME
PIN TYPE
DESCRIPTION
ALZ PIN
DDR0_CKN
IO
DDRSS Differential Clock (negative)
R1
DDR0_CKP
IO
DDRSS Differential Clock (positive)
P1
DDR0_RESETn
IO
DDRSS Reset
R5
DDR0_RET
I
DDR Retention Enable
T8
DDR0_CA0
IO
DDRSS Command Address
P3
DDR0_CA1
IO
DDRSS Command Address
P5
DDR0_CA2
IO
DDRSS Command Address
N5
DDR0_CA3
IO
DDRSS Command Address
P2
DDR0_CA4
IO
DDRSS Command Address
P4
DDR0_CA5
IO
DDRSS Command Address
R3
DDR0_CAL0(1)
A
IO Pad Calibration Resistor
R8
DDR0_CKE0
IO
DDRSS Clock Enable
R2
DDR0_CKE1
IO
DDRSS Clock Enable
R4
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TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1
SPRSP62 – DECEMBER 2022
Copyright © 2023 Texas Instruments Incorporated
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