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TDA4AL...ALZQ1 数据表(PDF) 13 Page - Texas Instruments

部件名 TDA4AL...ALZQ1
功能描述  TDA4VE TDA4AL TDA4VL Jacinto™ Processors, Silicon Revision 1.0
PDF  251 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TDA4AL...ALZQ1 数据表(HTML) 13 Page - Texas Instruments

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Table 6-2. Pin Attributes (ALZ Package) (continued)
Ball
Num [1]
Ball
Name [2]
PADCFG Register [13]
PADCFG Address [14]
Signal
Name [3]
Mux
Mode [4]
Signal
Type [5]
I/O
Voltage [6]
Ball State
DURING
Reset
(RX/TX/PULL) [7]
Ball State
AFTER
Reset
(RX/TX/PULL) [8]
Mux
Mode
AFTER
Reset [9]
Power [10]
Voltage
Buffer
Type [11]
IO
RET [12]
R4
DDR0_CKE1
DDR0_CKE1
IO
1.1 V
VDDS_DDR /
VDDS_DDR_C
0
DDR
V5
DDR0_CSn0_0
DDR0_CSn0_0
IO
1.1 V
VDDS_DDR /
VDDS_DDR_C
0
DDR
W5
DDR0_CSn0_1
DDR0_CSn0_1
IO
1.1 V
VDDS_DDR /
VDDS_DDR_C
0
DDR
T5
DDR0_CSn1_0
DDR0_CSn1_0
IO
1.1 V
VDDS_DDR /
VDDS_DDR_C
0
DDR
U6
DDR0_CSn1_1
DDR0_CSn1_1
IO
1.1 V
VDDS_DDR /
VDDS_DDR_C
0
DDR
H5
DDR0_DM0
DDR0_DM0
IO
1.1 V
VDDS_DDR /
VDDS_DDR_C
0
DDR
M3
DDR0_DM1
DDR0_DM1
IO
1.1 V
VDDS_DDR /
VDDS_DDR_C
0
DDR
U4
DDR0_DM2
DDR0_DM2
IO
1.1 V
VDDS_DDR /
VDDS_DDR_C
0
DDR
AD1
DDR0_DM3
DDR0_DM3
IO
1.1 V
VDDS_DDR /
VDDS_DDR_C
0
DDR
F3
DDR0_DQ0
DDR0_DQ0
IO
1.1 V
VDDS_DDR /
VDDS_DDR_C
0
DDR
G4
DDR0_DQ1
DDR0_DQ1
IO
1.1 V
VDDS_DDR /
VDDS_DDR_C
0
DDR
F5
DDR0_DQ2
DDR0_DQ2
IO
1.1 V
VDDS_DDR /
VDDS_DDR_C
0
DDR
F1
DDR0_DQ3
DDR0_DQ3
IO
1.1 V
VDDS_DDR /
VDDS_DDR_C
0
DDR
J4
DDR0_DQ4
DDR0_DQ4
IO
1.1 V
VDDS_DDR /
VDDS_DDR_C
0
DDR
H3
DDR0_DQ5
DDR0_DQ5
IO
1.1 V
VDDS_DDR /
VDDS_DDR_C
0
DDR
J2
DDR0_DQ6
DDR0_DQ6
IO
1.1 V
VDDS_DDR /
VDDS_DDR_C
0
DDR
www.ti.com
TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1
SPRSP62 – DECEMBER 2022
Copyright © 2023 Texas Instruments Incorporated
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