TDA4AL...ALZQ1 datasheet(125/251 Pages) TI

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VDDSHV5 supports MMC1 signaling for SD memory cards. A dual voltage (3.3 V/1.8 V) power rail is required for compliant, high-speed

SD card operations. If compliant high-speed SD card operation is needed, then an independent, dual voltage (3.3 V/1.8 V) power

source and rail are required. The start of ramp-down from 3.3 V/1.8 V will be same as other 3.3-V domains as shown. If SD card is not

needed or standard data rates with fixed 3.3-V operation is acceptable, then domain can be grouped with digital IO 3.3-V power rail. If a

SD card is capable of operating with fixed 1.8 V, then domain can be grouped with digital IO 1.8-V power rail.

VDDA_3P3_USB is 3.3-V analog domain used for USB 2.0 differential interface signaling. A low noise, analog supply is recommended

to provide best signal integrity for USB data eye mask compliance. The start of ramp-down from 3.3 V will be same as other 3.3-V

domains as shown. If USB interface is not needed or data bit errors can be tolerated, then domain can be grouped with 3.3-V digital IO

power rail either directly or through a supply filter.

VDDA_1P8_<clk/pll/ana> are 1.8-V analog domains supporting clock oscillator, PLL and analog circuitry needing a low noise supply

for optimal performance. It is not recommended to combine digital VDDSHVn_MCU and VDDSHVn IO domains since high frequency

switching noise could negatively impact jitter performance of clock, PLL and DLL signals. Combining analog VDDA_1p8_<phy>

domains should be avoided but if grouped, then in-line ferrite bead supply filtering is required.

VDDA_1P8_<phy> are 1.8-V analog domains supporting multiple serial PHY interfaces. A low noise, analog supply is recommended

to provide best signal integrity, interface performance and spec compliance. If any of these interfaces are not needed, data bit errors

or non-compliant operation can be tolerated, then domains can be grouped with digital IO 1.8-V power rail either directly or through an

in-line supply filter is allowed.

VDDA_0P8_<dll/pll> are 0.8-V analog domains supporting PLL and DLL circuitry needing a low noise supply for optimal performance.

It is not recommended to combine these domains with any other 0.8-V domains since high frequency switching noise could negatively

impact jitter performance of PLL and DLL signals.

VDD_MCU is a digital voltage domain with a wide range enabling it to be grouped and ramped-up with either 0.8-V VDD_CORE or

0.85V RAM array (VDDAR_xxx) domains.

MCU_PORz and PORz must be asserted low for TΔ1 = 200 us MIN to ensure SoC resources enter into safe state before any voltage

begins to ramp down.

Figure 7-6. Isolated MCU and Main Domains, Primary Power- Down Sequencing

7.10.2.6 Independent MCU and Main Domains, Entry and Exit of MCU Only Sequencing

Entry into MCU Only state is accomplished by executing a power down sequence except for the 4 MCU domains

that remain energized. Exit from MCU Only state is accomplished by executing a power up sequence with the 4

MCU domains remaining energized throughout the seque.

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TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1

SPRSP62 – DECEMBER 2022

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