TDA4AL...ALZQ1 datasheet(166/251 Pages) TI

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GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME,

RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/

WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND,

TIMEOUTSTARTVALUE, WRDATAONADMUXBUS)

(4)

For 100 MHz:

•

CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = MAIN_PLL2_HSDIV1_CLKOUT / 3

For 133 MHz:

•

CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = MAIN_PLL0_HSDIV3_CLKOUT

7.10.5.10.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode

NO.(2) PARAMETER

DESCRIPTION

MODE(19)

MIN

MAX

MIN

MAX UNI

100 MHz(20)

133 MHz(20)

tc(clk)

Period, output clock GPMC_CLK(18)

div_by_1_mode;

; GPMC_FCLK_MUX;

TIMEPARAGRANULA

RITY_X1

7.52

tw(clkH)

Typical pulse duration, output clock

GPMC_CLK high

div_by_1_mode

; GPMC_FCLK_MUX;

TIMEPARAGRANULA

RITY_X1

0.475*P

(15)- 0.3

0.475*P

(15)- 0.3

tw(clkL)

Typical pulse duration, output clock

GPMC_CLK low

div_by_1_mode

; GPMC_FCLK_MUX;

TIMEPARAGRANULA

RITY_X1

0.475*P

(15)- 0.3

0.475*P

(15)- 0.3

td(clkH-csnV)

Delay time, output clock GPMC_CLK rising

edge to output chip select GPMC_CSn[i]

transition(14)

div_by_1_mode

; GPMC_FCLK_MUX;

TIMEPARAGRANULA

RITY_X1

no extra_delay

F(6)- 2.2

F+3.75 F(6)- 2.2

F(6)+

3.75

td(clkH-CSn[i]V)

Delay time, output clock GPMC_CLK rising

edge to output chip select GPMC_CSn[i]

invalid(14)

div_by_1_mode

; GPMC_FCLK_MUX;

TIMEPARAGRANULA

RITY_X1

no extra_delay

E(5)- 2.2

E(5)+

3.75

E(5)- 2.2

E(5)+

3.75

td(aV-clk)

Delay time, output address GPMC_A[27:1]

valid to output clock GPMC_CLK first edge

div_by_1_mode

; GPMC_FCLK_MUX;

TIMEPARAGRANULA

RITY_X1

B(2)-2.3 B(2)+4.5

B(2)-2.3 B(2)+4.5 ns

td(clkH-aIV)

Delay time, output clock GPMC_CLK rising

edge to output address GPMC_A[27:1]

invalid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULA

RITY_X1

–2.3

4.5

–2.3

4.5 ns

td(be[x]nV-clk)

Delay time, output lower byte enable and

command latch enable GPMC_BE0n_CLE,

output upper byte enable GPMC_BE1n

valid to output clock GPMC_CLK first edge

div_by_1_mode

; GPMC_FCLK_MUX;

TIMEPARAGRANULA

RITY_X1

B(2)-2.3 B(2)+1.9

B(2)-2.3 B(2)+1.9 ns

td(clkH-be[x]nIV)

Delay time, output clock GPMC_CLK rising

edge to output lower byte enable and

command latch enable GPMC_BE0n_CLE,

output upper byte enable GPMC_BE1n

invalid(11)

div_by_1_mode

; GPMC_FCLK_MUX;

TIMEPARAGRANULA

RITY_X1

D(4)-2.3 D(4)+1.9

D(4)-2.3 D(4)+1.9 ns

td(clkL-be[x]nIV)

Delay time, GPMC_CLK falling edge

to GPMC_BE0n_CLE, GPMC_BE1n

invalid(12)

div_by_1_mode

; GPMC_FCLK_MUX;

TIMEPARAGRANULA

RITY_X1

D(4)-2.3 D(4)+1.9

D(4)-2.3 D(4)+1.9 ns

td(clkL-be[x]nIV).

Delay time, GPMC_CLK falling edge

to GPMC_BE0n_CLE, GPMC_BE1n

invalid(13)

div_by_1_mode

; GPMC_FCLK_MUX;

TIMEPARAGRANULA

RITY_X1

D(4)-2.3 D(4)+1.9

D(4)-2.3 D(4)+1.9 ns

TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1

SPRSP62 – DECEMBER 2022

www.ti.com

166

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