TDA4AL...ALZQ1 datasheet(175/251 Pages) TI

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(3)

The FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC

functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by

active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.

(4)

P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(6)

(5)

H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(6)

(6)

GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

(7)

For div_by_1_mode:

•

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:

–

GPMC_CLK frequency = GPMC_FCLK frequency

•

CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz

•

GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/

WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,

OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,

WRDATAONADMUXBUS)

7.10.5.10.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode

NO.

PARAMETER

DESCRIPTION

MODE(15)

MIN

MAX

UNIT

133 MHz(16)

FA0

tw(be[x]nV)

Pulse duration, output lower-byte enable and

command latch enable GPMC_BE0n_CLE, output

upper-byte enable GPMC_BE1n valid time

Read

N(12)

Write

N(12)

FA1

tw(csnV)

Pulse duration, output chip select GPMC_CSn[i](13)

low

Read

A(1)

Write

A(1)

FA3

td(csnV-advnIV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output address valid and address latch

enable GPMC_ADVn_ALE invalid

Read

B(2)- 2.55 B(2)+ 2.65

Write

B(2)- 2.55 B(2)+ 2.65

FA4

td(csnV-oenIV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output enable GPMC_OEn_REn invalid

(Single read)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_

C(3)- 2.55 C(3)+ 2.65

FA9

td(aV-csnV)

Delay time, output address GPMC_A[27:1] valid to

output chip select GPMC_CSn[i](13) valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_

J(9)- 2.55 J(9)+ 2.65

FA10 td(be[x]nV-csnV)

Delay time, output lower-byte enable and

command latch enable GPMC_BE0n_CLE, output

upper-byte enable GPMC_BE1n valid to output

chip select GPMC_CSn[i](13) valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_

J(9)- 2.55 J(9)+ 2.65

FA12 td(csnV-advnV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output address valid and address latch

enable GPMC_ADVn_ALE valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_

K(10)- 2.55

K(10)+

2.65

FA13 td(csnV-oenV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output enable GPMC_OEn_REn valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_

L(11)- 2.55

L(11)+

2.65

FA16 tw(aIV)

Pulse duration output address GPMC_A[26:1]

invalid between 2 successive read and write

accesses

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_

G(7)

FA18 td(csnV-oenIV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output enable GPMC_OEn_REn invalid

(Burst read)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_

I(8)- 2.55 I(8)+ 2.65

FA20 tw(aV)

Pulse duration, output address GPMC_A[27:1]

valid - 2nd, 3rd, and 4th accesses

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_

D(4)

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TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1

SPRSP62 – DECEMBER 2022

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