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TDA4AL...ALZQ1 数据表(PDF) 222 Page - Texas Instruments |
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TDA4AL...ALZQ1 数据表(HTML) 222 Page - Texas Instruments |
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222 / 251 page ![]() NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT O6 td(CLK-D) Delay time, CLK active edge to D[i:0] transition(1) 1.8V, OSPI0 DDR TX; 1.8V, OSPI1 DDR TX –7.71 –1.56 ns 3.3V, OSPI0 DDR TX; 3.3V, OSPI1 DDR TX –7.71 –1.56 ns (1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1 (2) P = CLK cycle time = SCLK period (3) N = OSPI_DEV_DELAY_REG[D_INIT_FLD] (4) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD] (5) R = refclk OSPI_CLK OSPI_TIMING_01 OSPI_CSn O6 O6 O4 O3 O2 O1 O5 OSPI_D[i:0] Figure 7-101. OSPI Switching Characteristics – DDR TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1 SPRSP62 – DECEMBER 2022 www.ti.com 222 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1 |
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