TDA4AL...ALZQ1 datasheet(238/251 Pages) TI

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leakage current is 10 nA, or zero. Using an input leakage of zero with the resistor values given above, the result

is a minimum trigger threshold of 4.008 V.

This example demonstrates a system power supply voltage trip point that ranges from 4.008 V to 4.523 V.

Approximately 250 mV of this range is introduced by VMON1_ER_VSYS input threshold accuracy of ±3%,

approximately 150 mV of this range is introduced by resistor tolerance of ±1%, and approximately 100 mV of this

range is introduced by loading error when VMON1_ER_VSYS input leakage current is 2.5 μA.

The resistor values selected in this example produces approximately 100 μA of bias current through the resistor

divider when the system supply is 4.5 V. The 100 mV of loading error mentioned above could be reduced to

about 10 mV by increasing the bias current through the resistor divider to approximately 1 mA. So resistor

divider bias current vs loading error is something the system designer needs to consider when selecting

component values.

The system designer should also consider implementing a noise filter on the voltage divider output since

VMON1_ER_VSYS has minimum hysteresis and a high-bandwidth response to transients. This could be done

by installing a capacitor across R1 as shown in Figure 8-5. However, the system designer must determine the

response time of this filter based on system supply noise and expected response to transient events.

Figure 8-5 presents an example, when the system power supply voltage is nominally 5 V and the desired trigger

threshold is -10% or 4.5 V.

Device

VMON_VSYS

SPRSP56_VMON_ER_MON_01

VSS

4.81 k

Ω

40.2 k

Ω ±

VSYS

Value = Determined by system designer

(System Power Supply)

Figure 8-5. System Supply Monitor Voltage Divider Circuit

The VMON2_IR_VCPU pin provides a way to monitor VDD_CPU power supply. Must be externally connected as

close as possible to VDD_CPU pin on the board. SoCs that have a VMON6_IR_VEXT0P8 can optionally monitor

other domains such as VDD_CORE or VDD_MCU. Similarly, those signals should be as close as possible to

VDD_CORE or VDD_MCU pin on the board.

The VMON3_IR_VEXT1P8 and VMON4_IR_VEXT1P8 pins provide a way to monitor an external 1.8-V power

supply. The VMON5_IR_VEXT3P3 pin provides a way to monitor an external 3.3-V power supply. An internal

resistor divider with software control is implemented inside the SoC. Software can program the internal resistor

divider to create appropriate under voltage and over voltage interrupts. These pins should not be sourced from

an external resistor divider. If the monitored voltage requires adjustment, be sure to buffer the divided voltage

prior connecting to monitor pin.

8.2.5 High Speed Differential Signal Routing Guidance

The High Speed Interface Layout Guidelines provides guidance for successful routing of the high speed

differential signals. This includes PCB stackup and materials guidance as well as routing skew, length and

spacing limits. TI supports only designs that follow the board design guidelines contained in the application

report.

TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1

SPRSP62 – DECEMBER 2022

www.ti.com

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