KSZ9563RNXC datasheet(54/226 Pages) MICROCHIP

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KSZ9563R

DS00002419D-page 54

 2017-2018 Microchip Technology Inc.

4.9.3

MII MANAGEMENT (MIIM) INTERFACE

The device supports the IEEE 802.3 MII management interface, also known as the management data input/output

(MDIO) interface. This interface allows upper-layer devices to monitor and control the states of the KSZ9563R PHY

blocks, but it does not provide access to the switch registers. An external device with MDC/MDIO capability can read

the PHY status or configure the PHY settings. Details on the MIIM interface can be found in Clauses 22 and 45 of the

IEEE 802.3 Specification.

Use of MIIM conflicts with use of the In-Band Management interface. These interfaces cannot be used simultaneously.

The MIIM interface consists of the following:

• A physical connection that uses a data signal (MDIO) and a clock signal (MDC) for communication between an

external controller and the KSZ9563R. Note that the MDIO signal is open-drain.

• A specific protocol that operates across the two signal physical connection that allows an external controller to

communicate with the internal PHY devices.

• Access to a set of standard, vendor-specific and extended (MMD) 16-bit registers. These registers are also

directly accessible via the SPI and I2C interface options.

The MIIM Interface can operate up to a maximum clock speed of 5MHz. Access is limited to only the registers in the

PHY blocks of ports 1 and 2. Table 4-25 summarizes the MII management interface frame format.

The MIIM PHY address to PHY port mapping is as follows:

• PHY Address 1h to PHY port 1

• PHY Address 2h to PHY port 2

The MIIM register address space consists of two distinct areas.

• Standard MIIM Registers (Direct)

• MDIO Manageable Device (MMD) Registers (Indirect)

FIGURE 4-15:

BURST REGISTER WRITE

FIGURE 4-16:

BURST REGISTER READ

TABLE 4-25:

MII MANAGEMENT INTERFACE FRAME FORMAT

Operation

Mode

Preamble

(32-bit)

Start of

Frame

(2-bit)

Operation

Code

(2-bit)

PHY

Address

(5-bit)

Address

(5-bit)

Turn

Around

(2-bit)

Data

(16-bit)

Idle

Read

All 1s

A[4:0]

Reg[4:0]

D[15:0]

Write

All 1s

A[4:0]

Reg[4:0]

D[15:0]

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