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KSZ9563RNXC 数据表(PDF) 66 Page - Microchip Technology |
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KSZ9563RNXC 数据表(HTML) 66 Page - Microchip Technology |
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66 / 226 page  KSZ9563R DS00002419D-page 66 2017-2018 Microchip Technology Inc. 5.1.1.5 PME Pin Control Register 5.1.1.6 Global Chip ID 4 Register 5.1.1.7 Global Interrupt Status Register This register provides the top level interrupt status for the LUE and GPIO trigger and timestamp functions. These inter- rupts are enabled in the Global Interrupt Mask Register. For port specific interrupts, refer to the Port Interrupt Status Register. Address: 0x0006 Size: 8 bits Bits Description Type Default 7:2 RESERVED RO - 1 PME Pin Output Enable 0 = Disabled 1 = Enabled R/W 0b 0 PME Pin Output Polarity 0 = PME is active low 1 = PME is active high R/W 0b Address: 0x000F Size: 8 bits Bits Description Type Default 7:0 SKU ID RO 0x1C Address: 0x0010 - 0x0013 Size: 32 bits Bits Description Type Default 31 Lookup Engine (LUE) Interrupt Status Refer to the Address Lookup Table Interrupt Register for detailed LUE interrupt status bits. 0 = No interrupt 1 = Interrupt request RO 0b 30 GPIO Pin Output Trigger and Timestamp Unit Interrupt Status Refer to the GPIO Status Monitor 1 Register to determine whether it is a Trigger Output Unit interrupt or a Timestamp Unit interrupt. For the interrupt status for the port-based time stamping of PTP egress frames, refer to the Port Interrupt Status Register and Port PTP Timestamp Interrupt Status Register. 0 = No interrupt 1 = Interrupt request RO 0b 29:0 RESERVED RO - |
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