KSZ9563RNXC datasheet(58/226 Pages) MICROCHIP

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KSZ9563R

DS00002419D-page 58

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4.11.1

MEDIA INDEPENDENT INTERFACE (MII)

The media independent interface (MII) is specified in Clause 22 of the IEEE 802.3 standard. It provides a common inter-

face between PHY layer and MAC layer devices. The data interface is 4-bits wide and runs at one quarter the network

bit rate; either 2.5MHz in 10BASE-T or 25MHz in 100BASE-TX (not encoded). Additional signals on the transmit side

indicate when data is valid or when an error occurs during transmission. Similarly, the receive side provides signals that

convey when the data is valid and without physical layer errors. For half duplex operation, the COL signal indicates if a

collision has occurred during transmission.

The MII interface operates in either PHY Mode or MAC Mode. Select PHY Mode when the port is connected to a pro-

cessor or other device with a MAC function; select MAC Mode when connecting to an external PHY. Note that the direc-

tion of the TX_CLK and RX_CLK signals is affected by the PHY mode or MAC mode setting, while other MII signals

do not change direction.

MII mode is selected at reset by a configuration strap option on pins RXD3 and RXD2. The Speed strapping option (on

pin LED2_1) should be set for 100/10 Mbps Mode. PHY Mode or MAC Mode is selected by strapping option on pin

LED2_0. Refer to Section 3.2.1, "Configuration Straps," on page 16 for additional information.

The interface contains two distinct groups of signals, one for transmission and the other for reception. Table 4-27 and

Table 4-28 describe the signals used by the MII interface to connect to an external MAC or to an external PHY, respec-

tively.

4.11.2

REDUCED MEDIA INDEPENDENT INTERFACE (RMII)

The reduced media independent interface (RMII) specifies a low pin count interface, which is based on MII, that provides

communication with a MAC attached to the port. As with MII, RMII provides a common interface between physical layer

and MAC layer devices, or between two MAC layer devices, and has the following key characteristics:

• Supports network data rates of either 10Mbps or 100Mbps.

• Uses a single 50MHz clock reference (provided internally or externally) for both transmit and receive data.

• Uses independent 2-bit wide transmit and receive data paths.

• Contains two distinct groups of signals: one for transmission and the other for reception.

The user selects one of the two RMII clocking modes by setting the appropriate strapping option.

TABLE 4-27:

MII (PHY MODE) CONNECTION TO EXTERNAL MAC

MII Interface Signals Description

KSZ9563R Signals in PHY Mode

External MAC Device Signals

Transmit Enable

TX_EN (input)

TX_EN (output)

Transit Error

TX_ER (input)

TX_ER (output)

Transmit Data Bits [3:0]

TXD[3:0] (input)

TXD[3:0] (output)

Transmit Clock

TX_CLK (output)

TX_CLK (input)

Received Data Valid

RX_DV (output)

RX_DV (input)

Receive Error

RX_ER (output)

RX_ER (input)

Receive Data Bits [3:0]

RXD[3:0] (output)

RXD[3:0] (input)

Receive Clock

RX_CLK (output)

RX_CLK (input)

TABLE 4-28:

MII (MAC MODE) CONNECTION TO EXTERNAL PHY

MII Interface Signals Description

KSZ9563R Signals in MAC Mode

External PHY Device Signals

Transmit Enable

RX_DV (output)

TX_EN (input)

Transit Error

RX_ER (output)

TX_ER (input)

Transmit Data Bits [3:0]

RXD[3:0] (output)

TXD[3:0] (input)

Transmit Clock

RX_CLK (input)

TX_CLK (output)

Received Data Valid

TX_EN (input)

RX_DV (output)

Receive Error

TX_ER (input)

RX_ER (output)

Receive Data Bits [3:0]

TXD[3:0] (input)

RXD[3:0] (output)

Receive Clock

TX_CLK (input)

RX_CLK (output)

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