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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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KSZ9563RNXC 数据表(PDF) 158 Page - Microchip Technology |
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KSZ9563RNXC 数据表(HTML) 158 Page - Microchip Technology |
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158 / 226 page  KSZ9563R DS00002419D-page 158 2017-2018 Microchip Technology Inc. 5.2.4.12 Port Queue 0 Egress Limit Control Register 5.2.4.13 Port Queue 1 Egress Limit Control Register 5.2.4.14 Port Queue 2 Egress Limit Control Register Address: 0xN420 Port N: 1-3 Size: 8 bits Bits Description Type Default 7 RESERVED RO 0b 6:0 Egress Data Rate Limit for Queue 0 Frames When egress rate limiting is configured to “port-based” via bit 3 of the Switch MAC Control 5 Register, only this register is used for setting. The Port Queue 1-3 Egress Limit Control Registers are used only for queue-based rate limiting. Note that the update will not take effect until the Port Queue 3 Egress Limit Control Register is written. R/W 0x00 Address: 0xN421 Port N: 1-3 Size: 8 bits Bits Description Type Default 7 RESERVED RO 0b 6:0 Egress Data Rate Limit for Queue 1 Frames Note that the update will not take effect until the Port Queue 3 Egress Limit Control Register is written. R/W 0x00 Address: 0xN422 Port N: 1-3 Size: 8 bits Bits Description Type Default 7 RESERVED RO 0b 6:0 Egress Data Rate Limit for Queue 2 Frames Note that the update will not take effect until the Port Queue 3 Egress Limit Control Register is written. R/W 0x00 |
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