KSZ9563RNXI datasheet(19/226 Pages) MICROCHIP

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DS00002419D-page 19

KSZ9563R

4.1.1.5

Adaptive Equalizer

In 1000BASE-T mode, the adaptive equalizer provides the following functions:

• Detection for partial response signaling

• Removal of NEXT and ECHO noise

• Channel equalization

Signal quality is degraded by residual echo that is not removed by the analog hybrid because of impedance mismatch.

The device uses a digital echo canceler to further reduce echo components on the receive signal.

In 1000BASE-T mode, data transmission and reception occurs simultaneously on all four pairs of wires (four channels).

This results in high-frequency cross-talk coming from adjacent wires. The device uses three NEXT cancelers on each

receive channel to minimize the cross-talk induced by the other three channels.

In 10BASE-T/100BASE-TX mode, the adaptive equalizer needs only to remove the inter-symbol interference and

recover the channel loss from the incoming data.

4.1.1.6

Trellis Encoder and Decoder

In 1000BASE-T mode, the transmitted 8-bit data is scrambled into 9-bit symbols and further encoded into 4D-PAM5

symbols. On the receiving side, the idle stream is examined first. The scrambler seed, pair skew, pair order and polarity

must be resolved through the logic. The incoming 4D-PAM5 data is then converted into 9-bit symbols and de-scrambled

into 8-bit data.

4.1.2

100BASE-TX TRANSCEIVER

4.1.2.1

100BASE-TX Transmit

The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI con-

version, and MLT3 encoding and transmission.

The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial

bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized

data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. An external ISET resis-

tor sets the output current for the 1:1 transformer ratio.

The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude

balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output driver is also incorporated into the 100BASE-

TX driver.

4.1.2.2

100BASE-TX Receive

The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and

clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.

The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted

pair cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer has to adjust its

characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on com-

parisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization.

This is an ongoing process and self-adjusts against environmental changes such as temperature variations.

Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used

to compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion

circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.

The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then

used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/

5B decoder. Finally, the NRZ serial data is converted to an MII format and provided as the input data to the MAC.

4.1.2.3

Scrambler/De-Scrambler

The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI)

and baseline wander. The scrambler is used only for 100BASE-TX.

Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). The scrambler

generates a 2047-bit non-repetitive sequence. Then the receiver de-scrambles the incoming data stream using the

same sequence as at the transmitter.

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