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KSZ9563RNXI 数据表(PDF) 60 Page - Microchip Technology |
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KSZ9563RNXI 数据表(HTML) 60 Page - Microchip Technology |
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60 / 226 page ![]() KSZ9563R DS00002419D-page 60 2017-2018 Microchip Technology Inc. 4.11.3 REDUCED GIGABIT MEDIA INDEPENDENT INTERFACE (RGMII) RGMII provides a common interface between RGMII PHYs and MACs, and has the following key characteristics: • Pin count is reduced from 24 pins for GMII to 12 pins for RGMII. • All speeds (10Mbps, 100Mbps and 1000Mbps) are supported at both half- and full-duplex. • Data transmission and reception are independent and belong to separate signal groups. • Transmit data and receive data are each four bits wide - a nibble. • In-Band Status is supported when connected to a compatible PHY. In RGMII operation, the RGMII pins function as follows: • The MAC sources the transmit reference clock, TX_CLK, at 125MHz for 1000Mbps, 25MHz for 100Mbps, and 2.5MHz for 10Mbps. • The PHY recovers and sources the receive reference clock, RX_CLK, at 125MHz for 1000Mbps, 25MHz for 100Mbps, and 2.5MHz for 10Mbps. • For 1000BASE-T, the transmit data, TXD[3:0], is presented on both edges of TX_CLK, and the received data, RXD[3:0], is clocked out on both edges of the recovered 125MHz clock, RX_CLK. • TX_ER and RX_ER are combined with TX_EN and RX_DV, respectively, to form TX_CTL and RX_CTL. These two RGMII control signals are valid at the falling clock edge. After power-up or reset, the device is configured to RGMII mode if the RXD3 and RXD2 configuration strap pins are set to “11”. Refer to Section 3.2.1, "Configuration Straps," on page 16 for available options. This device supports RGMII in- band status as described in Section 4.11.3.1, RGMII In-Band Status (IBS). If IBS is not used,a configuration strap option sets the speed of the RGMII interface at power-up to either 1000Mbps or 100Mbps. The XMII Port Control 0 Register and XMII Port Control 1 Register can override the configuration strap option and set the RGMII speed to either 1000, 100 or 10Mbps. If a non-IBS PHY is connected to the RGMII port, it should be ensured that the PHY link speed is fixed in order to avoid a mismatch to the RGMII speed. The device provides the option to add a minimum of 1.5ns internal delay to either TX_CLK or RX_CLK, via the RGMII Internal Delay control bits in the XMII Port Control 1 Register. This can reduce or eliminate the need to add trace delay to the clock signals on the printed circuit board. RGMII_ID_ig enables delay on TX_CLK, and the default is off. RGMII_ID_eg enables delay on RX_CLK, and the default is on. Users should also be aware of any internal clock delay that may be added by the connected RGMII device. TABLE 4-32: RGMII SIGNAL DESCRIPTIONS RGMII Signal Name (per spec) RGMII Signal (per KSZ9563R) Pin Direction (with respect to PHY, KSZ9563R) Pin Direction (with respect to MAC) RGMII Signal Description TXC TX_CLK Input Output Transmit Reference Clock (125MHz for 1000Mbps, 25MHz for 100Mbps, 2.5MHz for 10Mbps) TX_CTL TX_CTL Input Output Transmit Control TXD[3:0] TXD[3:0] Input Output Transmit Data [3:0] RXC RX_CLK Output Input Receive Reference Clock (125MHz for 1000Mbps, 25MHz for 100Mbps, 2.5MHz for 10Mbps) RX_CTL RX_CTL Output Input Receive Control RXD[3:0] RXD[3:0] Output Input Receive Data [3:0] |
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